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A survey of behavioral-level partitioning systems
Many approaches have been developed to partition a system's behavioral description before a structural implementation is synthesized. We highlight the foundations and motivations for behavioral partitioning. We survey behavioral partitioning approaches, discussing abstraction levels, goals, major steps, and key assumptions in each
Mirroring Mobile Phone in the Clouds
This paper presents a framework of Mirroring Mobile Phone in the Clouds (MMPC) to speed up data/computing intensive applications on a mobile phone by taking full advantage of the super computing power of the clouds. An application on the mobile phone is dynamically partitioned in such a way that the heavy-weighted part is always running on a mirrored server in the clouds while the light-weighted part remains on the mobile phone. A performance improvement (an energy consumption reduction of 70% and a speed-up of 15x) is achieved at the cost of the communication overhead between the mobile phone and the clouds (to transfer the application codes and intermediate results) of a desired application. Our original contributions include a dynamic profiler and a dynamic partitioning algorithm compared with traditional approaches of either statically partitioning a mobile application or modifying a mobile application to support the required partitioning
Recent Advances in Graph Partitioning
We survey recent trends in practical algorithms for balanced graph
partitioning together with applications and future research directions
Hardware-software codesign in a high-level synthesis environment
Interfacing hardware-oriented high-level synthesis to software development is a computationally hard problem for which no general solution exists. Under special conditions, the hardware-software codesign (system-level synthesis) problem may be analyzed with traditional tools and efficient heuristics. This dissertation introduces a new alternative to the currently used heuristic methods. The new approach combines the results of top-down hardware development with existing basic hardware units (bottom-up libraries) and compiler generation tools. The optimization goal is to maximize operating frequency or minimize cost with reasonable tradeoffs in other properties.
The dissertation research provides a unified approach to hardware-software codesign. The improvements over previously existing design methodologies are presented in the frame-work of an academic CAD environment (PIPE). This CAD environment implements a sufficient subset of functions of commercial microelectronics CAD packages. The results may be generalized for other general-purpose algorithms or environments.
Reference benchmarks are used to validate the new approach. Most of the well-known benchmarks are based on discrete-time numerical simulations, digital filtering applications, and cryptography (an emerging field in benchmarking). As there is a need for high-performance applications, an additional requirement for this dissertation is to investigate pipelined hardware-software systems\u27 performance and design methods. The results demonstrate that the quality of existing heuristics does not change in the enhanced, hardware-software environment
A partition methodology to develop data flow dominated embedded systems
Comunicação apresentada no International Workshop on Model-Based Methodologies for Pervasive and Embedded Software (MOMPES 2004), 1, Hamilton, Ontario, Canada, 15-18 June 2004.This paper proposes an automatic partition methodology oriented to develop
data flow dominated embedded systems. The target architecture is
CPU-based with reconfigurable devices on attached board(s), which closely
matches the PSM meta-model applied to system modelling. A PSM flow
graph was developed to represent the system during the partitioning process.
The partitioning task applies known optimization algorithms - tabu search
and cluster growth algorithms - which were enriched with new elements to
reduce computation time and to achieve higher quality partition solutions.
These include the closeness function that guides cluster growth algorithm,
which dynamically adapts to the type of object and partition under analysis.
The methodology was applied to two case studies, and some evaluation
results are presented
MECA: A Multi-agent Environment for Cognitive Agents
Many fully functional multi-agent systems have been developed and put to use over the past twenty years, but few of them have been developed to succesfully facilitate social research through the use of social agents. There are three important difficulties that must be dealt with to successfully create a social system for use in social research. First, the system must have an adaptable agent framework that can successfully make intuitive and deliberative decisions much like a human participant would. Secondly, the system must have a robust architecture that not only ensures its functioning no matter the simulation, but also provides an easily understood interface that researchers can interact with while running their simulations. Finally, the system must be effectively distributed to handle the necessary number of agents that social research requires to obtain meaningful results. This paper presents our work on creating a multi-agent simulation for social agents that overcomes these three difficulties
Space station automation of common module power management and distribution
The purpose is to automate a breadboard level Power Management and Distribution (PMAD) system which possesses many functional characteristics of a specified Space Station power system. The automation system was built upon 20 kHz ac source with redundancy of the power buses. There are two power distribution control units which furnish power to six load centers which in turn enable load circuits based upon a system generated schedule. The progress in building this specified autonomous system is described. Automation of Space Station Module PMAD was accomplished by segmenting the complete task in the following four independent tasks: (1) develop a detailed approach for PMAD automation; (2) define the software and hardware elements of automation; (3) develop the automation system for the PMAD breadboard; and (4) select an appropriate host processing environment
Multilevel Combinatorial Optimization Across Quantum Architectures
Emerging quantum processors provide an opportunity to explore new approaches
for solving traditional problems in the post Moore's law supercomputing era.
However, the limited number of qubits makes it infeasible to tackle massive
real-world datasets directly in the near future, leading to new challenges in
utilizing these quantum processors for practical purposes. Hybrid
quantum-classical algorithms that leverage both quantum and classical types of
devices are considered as one of the main strategies to apply quantum computing
to large-scale problems. In this paper, we advocate the use of multilevel
frameworks for combinatorial optimization as a promising general paradigm for
designing hybrid quantum-classical algorithms. In order to demonstrate this
approach, we apply this method to two well-known combinatorial optimization
problems, namely, the Graph Partitioning Problem, and the Community Detection
Problem. We develop hybrid multilevel solvers with quantum local search on
D-Wave's quantum annealer and IBM's gate-model based quantum processor. We
carry out experiments on graphs that are orders of magnitudes larger than the
current quantum hardware size, and we observe results comparable to
state-of-the-art solvers in terms of quality of the solution
Reduction of co-simulation runtime through parallel processing
During the design phase of modern digital and mixed signal devices, simulations are run to determine the fitness of the proposed design. Some of these simulations can take large amounts of time, thus slowing down the time to manufacture of the system prototype. One of the typical simulations that is done is an integration simulation that simulates the hardware and software at the same time. Most simulators used in this task are monolithic simulators. Some simulators do have the ability to have external libraries and simulators interface with it, but the setup can be a tedious task. This thesis proposes, implements and evaluates a distributed simulator called PDQScS, that allows for speed up of the simulation to reduce this bottleneck in the design cycle without the tedious separation and linking by the user. Using multiple processes and SMP machines a simulation run time reduction was found
FeladatfĂĽggĹ‘ felĂ©pĂtĂ©sű többprocesszoros cĂ©lrendszerek szintĂ©zis algoritmusainak kutatása = Research of synthesis algorithms for special-purpose multiprocessing systems with task-dependent architecture
Ăšj mĂłdszert Ă©s egy keretrendszert fejlesztettĂĽnk ki olyan speciális többprocesszoros struktĂşra tervezĂ©sĂ©re, amely lehetĹ‘vĂ© teszi a pipeline működtetĂ©st akkor is, ha a feladat-leĂrásban nincs hatĂ©konyan kihasználhatĂł párhuzamosság. A szintĂ©zis egy magas szintű nyelven (C, Java, stb.) adott feladatleĂrásbĂłl indul ki. Ezután dekompozĂciĂłs algoritmus megfelelĹ‘ szegmenseket kĂ©pez a program alapján. A szegmensek kĂvánt száma, a szegmenseket megvalĂłsĂtĂł processzorok fĹ‘bb tulajdonságai Ă©s a becsĂĽlt kommunikáciĂłs idĹ‘igĂ©nyek megadhatĂłk bemeneti paramĂ©terekkĂ©nt. KedvezĹ‘ pipeline felĂ©pĂtĂ©s cĂ©ljábĂłl a pipeline adatfolyamok magas szintű szintĂ©zisĂ©nek (HLS) mĂłdszertanát alkalmaztuk. Ezek az eszközök az ĂĽtemezĂ©s Ă©s az allokáciĂł rĂ©vĂ©n kĂsĂ©rlik meg az optimalizálást a szegmensekbĹ‘l kĂ©pzett adatfolyam gráfon. EzĂ©rt a kiadĂłdĂł többprocesszoros felĂ©pĂtĂ©s nem egy uniformizált processzor-rács, hanem a megoldandĂł feladatra formált struktĂşra, Ăgy feladatfĂĽggĹ‘nek nevezhetĹ‘. A mĂłdszer modularitása lehetĹ‘vĂ© teszi a dekompozĂciĂłs algoritmusnak Ă©s a HLS eszköznek a cserĂ©jĂ©t, mĂłdosĂtását az alkalmazási igĂ©nyektĹ‘l fĂĽggĹ‘en. A mĂłdszer kiĂ©rtĂ©kelĂ©se cĂ©ljábĂłl olyan HLS eszközt alkalmaztunk, amely a kĂvánt pipeline ĂşjraindĂtási periĂłdust bemeneti adatkĂ©nt tudja kezelni, Ă©s processzorok között egy optimalizált idĹ‘osztásos, arbitráciĂł-mentes sĂnrendszert hoz lĂ©tre. Ebben a struktĂşrában a kommunikáciĂł szervezĂ©sĂ©hez nincs szĂĽksĂ©g kĂĽlön szoftver támogatásra, ha a processzorok kĂ©pesek közvetlen adatforgalomra. | A new method and a framework tool has been developed for designing a special multiprocessing structure for making the pipeline function possible as a special parallel processing, even if there is no efficiently exploitable parallelism in the task description. The synthesis starts from a task description written in a high level language (C, Java, etc). A decomposing algorithm generates proper segments of this program. The desired number of the segments, the main properties of the processor set implementing the segments and the estimated communication time-demand can be given as input parameters. For constructing a pipeline structure, the high-level synthesis (HLS) methodology of pipelined datapaths is applied. These tools attempt to optimize by scheduling and allocating the dataflow graph generated from the segments Thus, the resulted structure is not a uniform processor grid, but it is shaped depending on the task, i.e. it can be called task-dependent. The modularity of the method permits the decomposition algorithm and the HLS tool to be replaced by other ones depending on the requirements of the application. For evaluating the method, a specific HLS tool is applied, which can accept the desired pipeline restart time as input parameter, and generates an optimized time shared simple arbitration-free bus system between the processing units. Therefore, there is no need for extra efforts to organize the communication, if the processing units can transfer data directly
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