Design of Low-Cost Energy Harvesting and Delivery Systems for Self-Powered Devices: Application to Authentication IC

This thesis investigates the development of low-cost energy harvesting and delivery systems for low-power low-duty-cycle devices. Initially, we begin by designing a power management scheme for on-demand power delivery. The baseline implementation is also used to identify critical challenges for low-power energy harvesting. We further propose a robust self-powered energy harvesting and delivery system (EHDS) design as a solution to achieve energy autonomy in standalone systems. The design demonstrates a complete ecosystem for low-overhead pulse-frequency modulated (PFM) harvesting while reducing harvesting window confinement and overall implementation footprint. Two transient-based models are developed for improved accuracy during design space exploration and optimization for both PFM power conversion and energy harvesting. Finally, a low-power authentication IC is demonstrated and projected designs for self-powered System-on-Chips (SoCs) are presented. The proposed designs are proto-typed in two test-chips in a 65nm CMOS process and measurement data showcase improved performance in terms of battery power, cold-start duration, passives (inductance and capacitance) needed, and end-to-end harvesting/conversion efficiency.Ph.D

High-Efficiency Low-Voltage Rectifiers for Power Scavenging Systems

Abstract Rectifiers are commonly used in electrical energy conversion chains to transform the energy obtained from an AC signal source to a DC level. Conventional bridge and gate cross-coupled rectifier topologies are not sufficiently power efficient, particularly when input amplitudes are low. Depending on their rectifying element, their power efficiency is constrained by either the forward-bias voltage drop of a diode or the threshold voltage of a diode-connected MOS transistor. Advanced passive rectifiers use threshold cancellation techniques to effectively reduce the threshold voltage of MOS diodes. Active rectifiers use active circuits to control the conduction angle of low-loss MOS switches. In this thesis, an active rectifier with a gate cross-coupled topology is proposed, which replaces the diode-connected MOS transistors of a conventional rectifier with low-loss MOS switches. Using the inherent characteristics of MOS transistors as comparators, dynamic biasing of the bulks of main switches and small pull-up transistors, the proposed self-supplied active rectifier exhibits smaller voltage drop across the main switches leading to a higher power efficiency compared to conventional rectifier structures for a wide range of operating frequencies in the MHz range. Delivery of high load currents is another feature of the proposed rectifier. Using the bootstrapping technique, single- and double-reservoir based rectifiers are proposed. They present higher power and voltage conversion efficiencies compared to conventional rectifier structures. With a source amplitude of 3.3 V, when compared to the gate cross-coupled topology, the proposed active rectifier offers power and voltage conversion efficiencies improved by up to 10% and 16% respectively. The proposed rectifier using the bootstrap technique, including double- and single-reservoir schemes, are well suited for very low input amplitudes. They present power and voltage conversion efficiencies of 75% and 76% at input amplitude of 1.0 V and maintain their high efficiencies over input amplitudes greater than 1.0V. Single-reservoir bootstrap rectifier also reduces die area by 70% compared to its double-reservoir counterpart.---------Résumé Les redresseurs sont couramment utilisés dans de nombreux systèmes afin de transformer l'énergie électrique obtenue à partir d'une source alternative en une alimentation continue. Les topologies traditionnelles telles que les ponts de diodes et les redresseurs se servant de transistors à grilles croisées-couplées ne sont pas suffisamment efficaces en terme d’énergie, en particulier pour des signaux à faibles amplitudes. Dépendamment de leur élément de redressement, leur efficacité en termes de consommation d’énergie est limitée soit par la chute de tension de polarisation directe d'une diode, soit par la tension de seuil du transistor MOS. Les redresseurs passifs avancés utilisent une technique de conception pour réduire la tension de seuil des diodes MOS. Les redresseurs actifs utilisent des circuits actifs pour contrôler l'angle de conduction des commutateurs MOS à faible perte. Dans cette thèse, nous avons proposé un redresseur actif avec une topologie en grille croisée-couplée. Elle utilise des commutateurs MOS à faible perte à la place des transistors MOS connectés en diode comme redresseurs. Le circuit proposé utilise: des caractéristiques intrinsèques des transistors MOS pour les montages comparateurs et une polarisation dynamique des substrats des commutateurs principaux supportés par de petits transistors de rappel. Le redresseur proposé présente des faibles chutes de tension à travers le commutateur principal menant à une efficacité de puissance plus élevée par rapport aux structures d’un redresseur conventionnel pour une large gamme de fréquences de fonctionnement de l’ordre des MHz. La conduction des courants de charge élevée est une autre caractéristique du redresseur proposé. En utilisant la méthode de bootstrap, des redresseurs à simple et à double réservoir sont proposés. Ils présentent une efficacité de puissance et un rapport de conversion de tension élevés en comparaison avec les structures des redresseurs conventionnels. Avec une amplitude de source de 3,3 V, le redresseur proposé offre des efficacités de puissance et de conversion de tension améliorées par rapport au circuit à transistors croisés couplés. Ces améliorations atteignent 10% et 16% respectivement. Les redresseurs proposés utilisent la technique de bootstrap. Ils sont bien adaptés pour des amplitudes d'entrée très basses. À une amplitude d'entrée de 1,0 V, ces derniers redresseurs présentent des rendements de conversion de puissance et de tension de 75% et 76%. Le redresseur à simple réservoir réduit également l’aire de silicium requise de 70% par rapport à la version à double-réservoir

RF Induced Nonlinear Effects in High-Speed Electronics

Previous experiments and research have indicated rectification of modulated electromagnetic interference can cause upset effects in digital electronics. Although RF rectification has been observed in discrete components, only speculation of the most sensitive mechanisms causing RF rectification has been proposed. Through theoretical analysis, experiments, and simulations, the p-n junctions in ESD protection circuits were determined to be susceptible to rectifying pulse modulated RF signals. Threshold experiments on several logic families of CMOS inverters provided indications to susceptibilities of electronics based on their input ESD protection topology. Parasitic elements have also been determined to cause additional effects including bias shifts, state changes, RF gain, and circuit resonances. DC and high frequency parameter extraction techniques were used to build diode and generic inverter models including package parasitics in PSPICE. Models were designed which gave good agreement to measured rectification drive curves, input impedance resonances, output voltage bias shifts, and induced spurious oscillations

High performance zero-crossing based pipelined analog-to-digital converters

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 133-137).As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow for more power ecient and faster digital circuits to be made. But at the same time, output impedance of transistors has gone down, as have the power supply voltages, and leakage currents have increased. These changes in the technology have made analog design more difficult. More specifically, the design of a high gain op-amp, a fundamental analog building block, has become more difficult in scaled processes. In this work, op-amps in pipelined ADCs are replaced with zero-crossing detectors(ZCD). Without the closed-loop feedback provided by the op-amp, a new set of design constraints for Zero-Crossing Based Circuits (ZCBC) is explored.by Yue Jack Chu.Ph.D

Development of a temperature insensitive current controlled current source for LNA bias circuit applications

The research described in this thesis is concerned with the analysis, design and development of a novel temperature insensitive Current Controlled Current Source (CCCS), in bipolar technology, in order to provide accurate amplification of a Proportional To Absolute Temperature (PTAT) reference current. The output current of the CCCS is intended for application as the bias current for a bipolar Low Noise Amplifier (LNA) in order to minimise gain variations with temperature across the industrial temperature range (-40·C to 8S·C). The thesis begins with an explanation of key parameters concerned with LNA design and a target specification is defined. In Chapter 2, a conventional LNA, with constant with temperature bias current, is developed following a methodical approach based on conventional techniques. This meets the previously defined specification at room temperature but exhibits large gain variations with changes in temperature. The analysis and simulation results of this conventional LNA serve as a benchmark for comparison with later designs. In order to minimise any gain variations with temperature of a bipolar amplifier it is well known that the applied bias current should be PT AT. Thus, a thorough analysis and comparative review of traditional and novel PTAT reference current generator circuits is conducted in Chapters 3 and 4. Based on these findings the PTAT generator exhibiting best performance in terms of output current accuracy and insensitivity to power supply variations is presented. However, this circuit cannot accurately produce large rnA level currents necessary for LNA bias applications so that sufficient linearity of the LNA is maintained. Thus, a need for some form of accurate CCCS or Voltage Controlled Current Source (VCCS), which should be temperature insensitive in order to preserve the desired temperature coefficient of the reference current/voltage, is highlighted. Traditional VCCS/CCCS designs are investigated in Chapter 5. Limitations of these approaches leads to the design and development ofa novel CCCS with built in PTAT reference. The presented CCCS utilises a new, previously unseen, architecture and has led to a patent application [1]. The author has reported the majority of this work in technical literature [2-4]. In Chapter 6, the output of the novel CCCS is adapted to include the conventional LNA circuit designed previously in Chapter 2. The results of the combined LNA and CCCS are compared with the conventional LNA. The combined LNA and CCCS offers a dramatic reduction in gain variation with temperature

Analysis and design on low-power multi-Gb/s serial links

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel

Advanced modelling and design considerations for interconnects in ultra- low power digital system

PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption for advanced System-on- Chip (SoC)s. However, the growing complexity of interconnects behaviour presents a challenge for their adequate modelling, whereby conventional circuit theoretic approaches cannot provide sufficient accuracy. During the last decades, fractional differential calculus has been successfully applied to modelling certain classes of dynamical systems while keeping complexity of the models under acceptable bounds. For example, fractional calculus can help capturing inherent physical effects in electrical networks in a compact form, without following conventional assumptions about linearization of non-linear interconnect components. This thesis tackles the problem of interconnect modelling in its generality to simulate a wide range of interconnection configurations, its capacity to emulate irregular circuit elements and its simplicity in the form of responsible approximation. This includes modelling and analysing interconnections considering their irregular components to add more flexibility and freedom for design. The aim is to achieve the simplest adaptable model with the highest possible accuracy. Thus, the proposed model can be used for fast computer simulation of interconnection behaviour. In addition, this thesis proposes a low power circuit for driving a global interconnect at voltages close to the noise level. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles. The major contributions of this thesis are twofold. Firstly, in order to address Ultra-Low Power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumption. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single event upset (SEU)s, which are known to affect DSM circuits working under low voltages. Secondly, the CMOS circuit driving a distributed RLC load has been brought in its analysis into the fractional order domain. This model will make the on-chip interconnect structure easy to adjust by including the effect of fractional orders on the interconnect timing, which has not been considered before. A second-order model for the transfer functions of the proposed general structure is derived, keeping the complexity associated with second-order models for this class of circuits at a minimum. The approach here attaches an important trait of robustness to the circuit design procedure; namely, by simply adjusting the fractional order we can avoid modifying the circuit components. This can also be used to optimise the estimation of the system’s delay for a broad range of frequencies, particularly at the beginning of the design flow, when computational speed is of paramount importance.Iraqi Ministry of Higher Education and Scientific Researc

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Efficient, low-distortion switch-mode power amplifier for amplitude modulation

Thesis (M. Eng.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February 2011.Cataloged from PDF version of thesis. "September 28, 2010."Includes bibliographical references (pages 85-87).Amplitude modulation systems are used in many areas of engineering, especially communication based disciplines. Typical systems have low-level signals which encode the desired information to be transmitted. These low-level signals are usually not of adequate power to transmit the desired information across a target medium, thus requiring modulation and power amplification. In general, two goals of power amplifier design are low-distortion and high-efficiency. To meet these goals, a unique switch-mode power amplifier intended for amplitude modulation which utilizes spectral content at the carrier frequency is designed, simulated, and built. Theoretical predictions of total harmonic distortion (THD) and efficiency are made, and the constructed prototype results are measured. The THD for a 1 kHz modulating tone is predicted to be 0.9% and measured to be 4.15% worst case. The amplifier output stage efficiency is predicted to be 95.8% and measured to be 95.4% worst case.by Christopher Buenrostro.M.Eng