Under-the-cell routing to improve manufacturability

The progressive miniaturization of technology and the unequal scalability of the BEOL and FEOL layers aggravate the routing congestion problem and have a negative impact on manufacturability. Standard cells are designed in a way that they can be treated as black boxes during physical design. However, this abstraction often prevents an efficient use of its internal free resources. This paper proposes an effective approach for using internal routing resources without sacrificing modularity. By using cell generation tools for regular layouts, libraries are enriched with cell instances that have lateral pins and allow under-the-cell connections between adjacent cells, thus reducing pin count, via count and routing congestion. An approach to generate cells with regular layouts and lateral pins is proposed. Additionally, algorithms to maximize the impact of under-the-cell routing are presented. The proposed techniques are integrated in an industrial design flow. Experimental results show a significant reduction of design rule check violations with negligible impact on timing.Peer ReviewedPostprint (author's final draft

Printed Circuit Board (PCB) design process and fabrication

This module describes main characteristics of Printed Circuit Boards (PCBs). A brief history of PCBs is introduced in the first chapter. Then, the design processes and the fabrication of PCBs are addressed and finally a study case is presented in the last chapter of the module.Peer ReviewedPostprint (published version

Power Management Techniques for Data Centers: A Survey

With growing use of internet and exponential growth in amount of data to be stored and processed (known as 'big data'), the size of data centers has greatly increased. This, however, has resulted in significant increase in the power consumption of the data centers. For this reason, managing power consumption of data centers has become essential. In this paper, we highlight the need of achieving energy efficiency in data centers and survey several recent architectural techniques designed for power management of data centers. We also present a classification of these techniques based on their characteristics. This paper aims to provide insights into the techniques for improving energy efficiency of data centers and encourage the designers to invent novel solutions for managing the large power dissipation of data centers.Comment: Keywords: Data Centers, Power Management, Low-power Design, Energy Efficiency, Green Computing, DVFS, Server Consolidatio

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning

Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5% in comparison to standard approaches

Prediction of springback in the forming of advanced high strength steel: simulation and experimental study

Dual Phase (DP) steel is categorized as advanced high-strength steels (AHSS) which has tensile strengths ranging from 500 to 800 MPa. DP steel is gaining popularity in automotive applications. It has higher formability than HSLA grades with similar initial yield strengths, but has much higher final part strength. With proper design strategy, Dual Phase (DP) steels offers a great advantage in terms of body weight reduction and crash performance. One of the major constraints in forming AHSS is the occurrence of high springback caused by elastic relaxation after loading, which causes ill-fitting in part assembly and geometric deviation of the intended design. This research focused on finite element (FE) simulation of the sheet forming of dual phase steel and the springback prediction. If springback could be accurately predicted, the forming die could be correctly designed to compensate springback. The material used in this study was DOCOL 800 DP manufactured by SSAB- Sweden with ultimate tensile strength of 870 MPa and thickness of 0.72mm. The plastic behavior of DP800 was presented by exponential based constitutive equation known as isotropic hardening. From tensile test, strain hardening value (n) was 0.308 and strength coefficient (K) was 1319.165 MP. The FE simulations were conducted for tensile test, U-channel forming and springback simulation. These simulations were carried out by using general purpose transient dynamic FE code Lsdyna. The tensile test simulation result indicated the isotropic hardening material model was suitable for DP800 behavior with standard deviation value 62.45 MPa between simulation and experiment. Meanwhile, the springback simulation using U-channel represented the deviation for BHF 10kN, 20kN, 30kN and 97kN were 0.019, 0.071, 0.341 and 0.231. Overall, the result of 20KN BHF applied indicated the minimum springback in the forming of DP800