Impact of intrinsic parameter fluctuations in ultra-thin body silicon-on-insulator MOSFET on 6-transistor SRAM cell

As CMOS device dimensions are being aggressively scaled, the device characteristic must be assessed against fundamental physical limits. Nanoscale device modelling and statistical circuit analysis is needed to provide designer with ability to explore innovative new MOSFET devices as well as understanding the limits of the scaling process. This work introduces a systematic simulation methodology to investigate the impact of intrinsic parameter fluctuation for a novel Ultra-Thin-Body (UTB) Silicon-on-Insulator (SOI) transistor on the corresponding device and circuits. It provides essential link between physical device-level numerical simulation and circuit-level simulation. A systematic analysis of the effects of random discrete dopants, body thickness variations and line edge roughness on a well scaled 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFET is performed. To fully realise the performance benefits of UTB-SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuations information into the compact model is developed. The impact of intrinsic parameter fluctuations on the stability and performance of 6T SRAM has been investigated. A comparison with the behaviour of a 6T SRAM based on a conventional 35 nm MOSFET is also presented

UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation

Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Ultra thin body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. To fully realise the performance benefits of UTB SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into the compact model is developed. The impact on 6T SRAM static noise margin characteristics of discrete random dopants in the source/drain regions and body-thickness variations has been investigated for well scaled devices with physical channel length in the range of 10nm to 5nm. A comparison with the behaviour of a 6T SRAM based on a conventional 35nm MOSFET is also presented

Monte Carlo investigation of optimal device architectures for SiGe FETs

Strained silicon channel FETs grown on virtual SiGe substrates show clear potential for RF applications, in a material system compatible with silicon VLSI. However, the optimisation of practical RF devices requires some care. 0.1-0.12 μm gate length designs are investigated using Monte Carlo techniques. Although structures based on III-V experience show fT values of up to 94 GHz, more realistic designs are shown to be limited by parallel conduction and ill constrained effective channel lengths. Aggressively scaled SiGe devices, following state-of-the-art CMOS technologies, show fT values of up to 80 GHz

The impact of random doping effects on CMOS SRAM cell

The SRAM has a very constrained cell area and is consequently sensitive to the intrinsic parameter fluctuations ubiquitous in decananometer scale MOSFETs. Using a statistical circuit simulation methodology, which can fully collate intrinsic parameter fluctuation information into compact model sets, the impact of random device doping on 6-T SRAM static noise margins, and read and write characteristics are investigated in detail for well-scaled 35 nm physical gate length devices. We conclude that intrinsic parameter fluctuations will become a major limitation to further conventional MOSFET SRAM scaling

RF analysis methodology for Si and SiGe FETs based on transient Monte Carlo simulation

A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed

Integrating 'atomistic', intrinsic parameter fluctuations into compact model circuit analysis

MOSFET parameter fluctuations, resulting from the 'atomistic' granular nature of matter, are predicted to be a critical roadblock to the scaling of devices in future electronic systems. A methodology is presented which allows compact model based circuit analysis tools to exploit the results of 'atomistic' device simulation, allowing investigation of the effects of such fluctuations on circuits and systems. The methodology is applied to a CMOS inverter, ring oscillator, and analogue NMOS current mirror as simple initial examples of its efficacy

Monte Carlo simulations of high-performance implant free In_0.3Ga_0.7 nano-MOSFETs for low-power CMOS applications

No abstract available

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed

Modelling and simulation of advanced semiconductor devices

This paper presents a modelling and simulation study of advanced semiconductor devices. Different Technology Computer Aided Design approaches and models, used in nowadays research are described here. Our discussions are based on numerous theoretical approaches starting from first principle methods and continuing with discussions based on more well stablished methods such as Drift-Diffusion, Monte Carlo and Non-Equilibrium Green’s Function formalism

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current