Accurate analytical modeling for switching energy of PiN diodes reverse recovery

PiN diodes are known to significantly contribute to switching energy as a result of reverse-recovery charge during turn-off. At high switching rates, the overlap between the high peak reserve-recovery current and the high peak voltage overshoot contributes to significant switching energy. The peak reverse-recovery current depends on the temperature and switching rate, whereas the peak diode voltage overshoot depends additionally on the stray inductance. Furthermore, the slope of the diode turn-off current is constant at high insulated-gate bipolar transistor (IGBT) switching rates and varies for low IGBT switching rates. In this paper, an analytical model for calculating PiN diode switching energy at different switching rates and temperatures is presented and validated by ultrafast and standard recovery diodes with different current ratings. Measurements of current commutation in IGBT/PiN diode pairs have been made at different switching rates and temperatures and used to validate the model. It is shown here that there is an optimal switching rate to minimize switching energy. The model is able to correctly predict the switching rate and temperature dependence of the PiN diode switching energies for different devices

Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

Analysis of dynamic performance and robustness of silicon and SiC power electronics devices

The emergence of SiC power devices requires evaluation of benefits and issues of the technology in applications. This is important since SiC power devices are still not as mature as their silicon counterparts. This research, in its own capacity, highlights some of the major challenges and analyzes them through extensive experimental measurements which are performed in many different conditions seeking to emulate various applications scenarios. It is shown that fast SiC unipolar devices, inherently reduce the switching losses while maintain low conduction losses comparable with contemporary bipolar technologies. This translates into lower temperature excursions and an enhanced conversion efficiency. However, such high switching rates may trigger problems in the device utilizations. The switching rates influenced by the device input capacitance can cause significant ringing in the output, especially in SiC SBDs. Measurements show that switching rate of MOSFETs increases with increasing temperature in turn on and reduces in turn off. Hence, the peak voltage overshoot and oscillation severity of the SiC SBD increases with temperature during diode turn off. This temperature dependence reduces at the higher switching rates. So accurate analytical models are developed for predicting the switching energy in unipolar SiC SBDs and MOSFET pairs and bipolar silicon PiN and IGBT pairs. A key parameter for power devices is electrothermal robustness. SiC MOSFETs have already demonstrated such merits compared to silicon IGBTs, however not for MOSFET body diodes. This research has quantified this in comparison with the similarly rated contemporary device technologies like CoolMOS. In a power MOSFET, high switching rates coupled with the capacitance of drain and body causes a displacement current in the resistive path of P body, inducing a voltage on base of the parasitic NPN BJT which might forward bias it. This may lead to latch up and destruction if the thermal limits are surpassed. Hence, trade offs between switching energy and electrothermal robustness are explored for the silicon, SiC and superjunction power MOSFETs. Measurements show that performance of body diodes of SiC MOSFETs is the most efficient due to least reverse recovery. The minimum forward current for inducing dynamic latch up decreases with increasing voltage, switching rate and temperature for all technologies. The CoolMOS exhibited the largest latch up current followed by the SiC and silicon power MOSFETs. Another problem induced by high switching rates is the electrical coupling between complementing devices in the same phase leg which manifests as short circuits across the DC link voltage. This has been understood for silicon IGBTs with known corrective techniques, however it is seen that due to smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot through currents in spite of higher switching rates and a lower threshold voltage. Measurements show that the shoot through current exhibits a positive temperature coefficient for both technologies the magnitude of which is higher for the silicon IGBT. The effectiveness of common techniques of mitigating shoot through is also evaluated, showing that solutions are less effective for SiC MOSFET because of the lower threshold voltages and smaller margins for a negative gate bias