Realization of a 10 kW MES power to methane plant based on unified AC/DC converter

This paper presents a galvanic isolated multi output AC/DC topology that is suitable for Microbial electrosynthesis (MES) based Power to Methane energy storage systems. The presented scheme utilizes a three phase back to back converters, a single-input and multiple-output three phase transformer, single diode rectifiers and buck converters that employ a proper interconnection between MES cells and the mains. The proposed topology merges all the required single phase AC/DC converters as a unified converter which reduces the overall system size and provides system integrity and overall controllability. The proposed control scheme allows to achieve the following desired goals:1) Simultaneous control of all cells; 2) Absorbing power from the grid and covert to methane when the electricity price goes down; 3) the power factor and the quality of grid current is under control; 4) Supplying MES cells at the optimal operating point. For verification of system performance, Real time simulation results that are obtained from a 10-kW MES energy storage are presented.Postprint (author's final draft

Energy-Efficient and Reliable Computing in Dark Silicon Era

Dark silicon denotes the phenomenon that, due to thermal and power constraints, the fraction of transistors that can operate at full frequency is decreasing in each technology generation. Moore’s law and Dennard scaling had been backed and coupled appropriately for five decades to bring commensurate exponential performance via single core and later muti-core design. However, recalculating Dennard scaling for recent small technology sizes shows that current ongoing multi-core growth is demanding exponential thermal design power to achieve linear performance increase. This process hits a power wall where raises the amount of dark or dim silicon on future multi/many-core chips more and more. Furthermore, from another perspective, by increasing the number of transistors on the area of a single chip and susceptibility to internal defects alongside aging phenomena, which also is exacerbated by high chip thermal density, monitoring and managing the chip reliability before and after its activation is becoming a necessity. The proposed approaches and experimental investigations in this thesis focus on two main tracks: 1) power awareness and 2) reliability awareness in dark silicon era, where later these two tracks will combine together. In the first track, the main goal is to increase the level of returns in terms of main important features in chip design, such as performance and throughput, while maximum power limit is honored. In fact, we show that by managing the power while having dark silicon, all the traditional benefits that could be achieved by proceeding in Moore’s law can be also achieved in the dark silicon era, however, with a lower amount. Via the track of reliability awareness in dark silicon era, we show that dark silicon can be considered as an opportunity to be exploited for different instances of benefits, namely life-time increase and online testing. We discuss how dark silicon can be exploited to guarantee the system lifetime to be above a certain target value and, furthermore, how dark silicon can be exploited to apply low cost non-intrusive online testing on the cores. After the demonstration of power and reliability awareness while having dark silicon, two approaches will be discussed as the case study where the power and reliability awareness are combined together. The first approach demonstrates how chip reliability can be used as a supplementary metric for power-reliability management. While the second approach provides a trade-off between workload performance and system reliability by simultaneously honoring the given power budget and target reliability