Development and modeling of a low temperature thin-film CMOS on glass

The push to develop integrated systems using thin-film transistors (TFT) on insulating substrates (i.e. glass) has always been limited due to low-mobility semiconducting films such as amorphous and polycrystalline silicon. Corning Incorporated is developing a new substrate material known as silicon-on-glass (SiOG). It is intrinsically better than amorphous and polycrystalline silicon materials due to its single crystal nature of the silicon film. This however does not mitigate the challenges associated with low temperature CMOS process and fabrication. The first generation of TFTs fabricated at RIT showed the potential of SiOG as a viable substrate material, but were plagued by considerable short comings such as high leakage and low transconductance. As part of this study, refinements to TFT processing on SiOG have demonstrated significant improvement to TFT performance and uniformity, showing increase transconductanace/mobility, lower subthreshold swing, tighter VT distributions, and near symmetrical NFET and PFET operation about 0 V. With these improvements minimal steps have been added to the manufacturing process, keeping simple and adoptable by the flat panel display (FPD) industry. Device modeling clearly demonstrates the key areas important to electrical operation, such as dopant activation, interface charge/trap reduction, and workfunction engineering. It addition, modeling and simulation have helped to explain the governing physics of device operation explaining non-ideal effects such as gate induced drain leakage (GIDL) and various mobility degradation mechanism. An overview of device design, process refinements and device operation is presented. Process modifications and resulting benefits are discussed along with CMOS integration on SiOG

On variability and reliability of poly-Si thin-film transistors

In contrast to conventional bulk-silicon technology, polysilicon (poly-Si) thin-film transistors (TFTs) can be implanted in flexible substrate and can have low process temperature. These attributes make poly-Si TFT technology more attractive for new applications, such as flexible displays, biosensors, and smart clothing. However, due to the random nature of grain boundaries (GBs) in poly-Si film and self-heating enhanced negative bias temperature instability (NBTI), the variability and reliability of poly-Si TFTs are the main obstacles that impede the application of poly-Si TFTs in high-performance circuits. The primary focus of this dissertation is to develop new design methodologies and modeling techniques for facilitating new applications of poly-Si TFT technology. In order to do that, a physical model is first presented to characterize the GB-induced transistor threshold voltage (V th)variations considering not only the number but also the position and orientation of each GB in 3-D space. The fast computation time of the proposed model makes it suitable for evaluation of GB-induced transistor Vthvariation in the early design phase. Furthermore, a self-consistent electro-thermal model that considers the effects of device geometry, substrate material, and stress conditions on NBTI is proposed. With the proposed modeling methodology, the significant impacts of device geometry, substrate, and supply voltage on NBTI in poly-Si TFTs are shown. From a circuit design perspective, a voltage programming pixel circuit is developed for active-matrix organic light emitting diode (AMOLED) displays for compensating the shift of Vth and mobility in driver TFTs as well as compensating the supply voltage degradation. In addition, a self-repair design methodology is proposed to compensate the GB-induced variations for liquid crystal displays (LCDs) and AMOLED displays. Based on the simulation results, the proposed circuit can decrease the required supply voltage by 20% without performance and yield degradation. In the final section of this dissertation, an optimization methodology for circuit-level reliability tests is explored. To effectively predict circuit lifetime, accelerated aging (i.e. elevated voltage and temperature) is commonly applied in circuit-level reliability tests, such as constant voltage stress (CVS) and ramp voltage stress (RVS) tests. However, due to the accelerated aging, shifting of dominant degradation mechanism might occur leading to the wrong lifetime prediction. To get around this issue, we proposed a technique to determine the proper stress range for accelerated aging tests

High-performance Zinc Oxide Thin-Film Transistors For Large Area Electronics

The increasing demand for high performance electronics that can be fabricated onto large area substrates employing low manufacturing cost techniques in recent years has fuelled the development of novel semiconductor materials such as organics and metal oxides, with tailored physical characteristics that are absent in their traditional inorganic counterparts such as silicon. Metal oxide semiconductors, in particular, are highly attractive for implementation into thin-film transistors because of their high charge carrier mobility, optical transparency, excellent chemical stability, mechanical stress tolerance and processing versatility. This thesis focuses on the development of high performance transistors based on zinc oxide (ZnO) semiconducting films grown by spray pyrolysis (SP), a low cost and highly scalable method that has never been used before for the manufacturing of oxide-based thin-film transistors. The physical properties of as-grown ZnO films have been studied using a range of techniques. Despite the simplicity of SP, as-fabricated transistors exhibit electrical characteristics comparable to those obtained from ZnO devices produced using highly sophisticated deposition processes. In particular, electron mobility up to 25 cm2/Vs has been achieved in transistors based on pristine ZnO films grown at 400 °C onto Si/SiO2 substrates utilising aluminium source-drain (S-D) electrodes. A strong dependence of the saturation mobility on the work function of S-D electrodes and the transistor channel length (L) has been established. Short channel transistors are found to exhibit improved performance as compared to long channel ones. This was attributed to grain boundary effects that tend to dominate charge transport in devices with L < 40 μm. High mobility, low operating voltage (<1.5 V) ZnO transistors have also been developed and characterised. This was achieved through the combination of SP, for the deposition of ZnO, and thermally stable solution-processed self-assembling monolayer gate dielectrics. Detailed study of the temperature dependence of the operating characteristics of ZnO transistors revealed a thermally activated electron transport process that was described by invoking the multiple trapping and release model. Importantly, ZnO transistors fabricated by SP are found to exhibit highly stable operating characteristics with a shelf lifetime of several months. The simple SPbased fabrication paradigm demonstrated in this thesis expands the possibilities for the development of advanced simple as well as multi-component oxide semiconductors far beyond those accessible by traditional deposition methods such as sputtering. Furthermore, it offers unprecedented processing scalability hence making it attractive for the manufacturing of future ubiquitous oxide electronics

Interpretation and Regulation of Electronic Defects in IGZO TFTs Through Materials & Processes

The recent rise in the market for consumer electronics has fueled extensive research in the field of display. Thin-Film Transistors (TFTs) are used as active matrix switching devices for flat panel displays such as LCD and OLED. The following investigation involves an amorphous metal-oxide semiconductor that has the potential for improved performance over current technology, while maintaining high manufacturability. Indium-Gallium-Zinc-Oxide (IGZO) is a semiconductor material which is at the onset of commercialization. The low-temperature large-area deposition compatibility of IGZO makes it an attractive technology from a manufacturing standpoint, with an electron mobility that is 10 times higher than current amorphous silicon technology. The stability of IGZO TFTs continues to be a challenge due to the presence of defect states and problems associated with interface passivation. The goal of this dissertation is to further the understanding of the role of defect states in IGZO, and investigate materials and processes needed to regulate defects to the level at which the associated influence on device operation is controlled. The relationships between processes associated with IGZO TFT operation including IGZO sputter deposition, annealing conditions and back-channel passivation are established through process experimentation, materials analysis, electrical characterization, and modeling of electronic properties and transistor behavior. Each of these components has been essential in formulating and testing several hypotheses on the mechanisms involved, and directing efforts towards achieving the goal. Key accomplishments and quantified results are summarized as follows: • XPS analysis identified differences in oxygen vacancies in samples before and after oxidizing ambient annealing at 400 °C, showing a drop in relative integrated area of the O 1s peak from 32% to 19%, which experimentally translates to over a thousand fold decrease in the channel free electron concentration. • Transport behavior at cryogenic temperatures identified variable range hopping as the electron transport mechanism at temperature below 130 K, whereas at temperature greater than 130 K, the current vs temperature response followed an Arrhenius relationship consistent with extended state transport. • Refinement of an IGZO material model for TCAD simulation, which consists of oxygen vacancy donors providing an integrated space charge concentration NVO = +5e15 cm-3, and acceptor-like band-tail states with a total integrated ionized concentration of NTA = -2e18 cm-3. An intrinsic electron mobility was established to be Un = 12.7 cm2/V∙s. • A SPICE-compatible 2D on-state operation model for IGZO TFTs has been developed which includes the integration of drain-impressed deionization of band-tail states and results in a 2D modification of free channel charge. The model provides an exceptional match to measured data and TCAD simulation, with model parameters for channel mobility (Uch = 12 cm2/V∙s) and threshold voltage (VT = 0.14 V) having a close match to TCAD analogs. • TCAD material and device models for bottom-gate and double-gate TFT configurations have been developed which depict the role of defect states on device operation, as well as provide insight and support of a presented hypothesis on DIBL like device behavior associated with back-channel interface trap inhomogeneity. This phenomenon has been named Trap Associated Barrier Lowering (TABL). • A process integration scheme has been developed that includes IGZO back-channel passivation with PECVD SiO2, furnace annealing in O2 at 400 °C, and a thin capping layer of alumina deposited via atomic layer deposition. This process supports device stability when subjected to negative and positive bias stress conditions, and thermal stability up to 140 °C. It also enables TFT operation at short channel lengths (Leff ~ 3 µm) with steep subthreshold characteristics (SS ~ 120 mV/dec). The details of these contributions in the interpretation and regulation of electronic defect states in IGZO TFTs is presented, along with the support of device characteristics that are among the best reported in the literature. Additional material on a complementary technology which utilizes flash-lamp annealing of amorphous silicon will also be described. Flash-Lamp Annealed Polycrystalline Silicon (FLAPS) has realized n-channel and p-channel TFTs with promising results, and may provide an option for future applications with the highest performance demands. IGZO is rapidly emerging as the candidate to replace a-Si:H and address the performance needs of display products produced by large panel manufacturing

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Investigation on solid-phase crystallization techniques for low temperature polysilicon thin-film transistors

Low-temperature polysilicon (LTPS) has emerged as a dominant technology for high performance thin-film transistors (TFTs) used in mobile liquid crystal display (LCD) and organic light emitting diode (OLED) display products. As users demand higher quality in flat panel displays with a larger viewing area and finer resolution, the improvement in carrier mobility of LTPS compared to that of hydrogenated amorphous silicon (a-Si:H) makes it an excellent candidate as a channel material for TFT. Advantages include improvements in switching speed and the ability to incorporate peripheral scan and data driver circuitry onto a low cost display substrate. Solid-phase crystallization (SPC) is a useful technique to realize polysilicon films due to its simplicity and low cost compared to excimer-laser annealing (ELA),which has many challenges in back-plane manufacturing on large glass panels.Metal induced crystallization (MIC) results in polycrystalline silicon films with grain size as large as tens of microns. Flash-lamp annealing (FLA) is a new and novel method to crystallize a-Si films at high temperature without distortion of the glass substrate by performing an annealing within millisecond range.This work investigates SPC, MIC and FLA techniques to realize LTPS films. In addition, TFTs were designed and fabricated to characterize the device quality of the semiconductor layer, and to compare the performance of different structural arrangements

Controlling morphology and molecular order of solution-processed organic semiconductors for transistors

As a potential low-cost alternative to traditional amorphous-silicon based devices, organic field-effect transistors (OFETs) are expected to be incorporated into all-plastic integrated circuits and flexible display backplanes. More recently, breakthroughs have been made in the performance of OFETs based on pi- conjugated small molecules, among which, tri-isopropylsilylethynyl pentacene (TIPS-PEN) and its derivatives are currently under extensive investigations due to their good charge-transport properties combined with decent air-stability, as well as the possibility of inexpensive solution-processing. Fundamental understanding of the charge transport is not only important to deepen the understanding of structure-property relationships of organic functional layers, but also to optimize the performance of various organic electronic devices. The charge-carrier mobility is a critical parameter for the operating speed of a device, notably, in an OFET. Structural inhomogeneity within a single component or between phase-separated blends has a significant impact on the local charge-transport properties. Thus, controlling the morphology and molecular order of organic semiconductors is the key to achieve optimal performance for OFETs. This thesis is aiming at highly reproducible solution-processed organic transistors, with device parameters relevant to practical applications (e.g. low operating-voltages, steep sub-threshold slopes and uniform performance in large areas), through controlling the morphology and molecular order of small-molecule organic semiconductors. More specifically, this thesis intends to achieve a balanced combination of (i) a solvent-based processing method that can manipulate the morphology of organic semiconductors; (ii) a composite semiconductor formulation consisting of TIPS-PEN and a binder material such as a polymer; (iii) use of patterning methods in line with the requirements of large-area electronics, such as ink-jet printing; and (iv) an improved understanding of charge-transport mechanisms in (realistic) high-performance transistor devices based on these single-component or composite semiconductors. This combination results in highly reproducible solution-processed OFETs exhibiting high mobility as well as decent uniformity in large areas, as demonstrated throughout the thesis. Aiming at the first objective (i) of this thesis, in Chapter 2, a new approach was developed to prepare large single crystals of organic semiconductors, by using azeotropic binary solvent mixtures. The two solvents form a positive azeotrope and have significantly different solubilities for TIPS-PEN. At solvent compositions close to the azeotropic point, an abrupt transition of morphology from polycrystalline thin-films to large single crystals was observed. We found that the solvent composition at the late-stage of evaporation determines the final morphology, which can be facilely controlled by adjusting the initial volume ratio of the binary solvents. The charge-carrier mobilities were substantially enhanced by a factor of 4, from the morphology of thin-films to large single crystals used as active layer in OFETs. Additionally, this approach was extended to other pi-conjugated organic molecules to elucidate its broad applicability. To achieve a balanced combination of the objectives (ii) &amp; (iii), i.e. large-area patterning of composite semiconductors, next, we set out to study the effects of blending an organic semiconductor with an insulating polymer on the morphology and transistor performance. In Chapter 3 we presented a systematic study of the influence of material composition and ink-jet processing conditions on the charge transport in bottom-gate/bottom-contact OFETs based on single droplets of TIPS-PEN/ polystyrene blends. After careful process optimization of blending ratio and printing temperature we routinely make transistors with an average mobility of 1 cm2/Vs (maximum 1.5 cm2/Vs), on/off ratio exceeding 107, sharp turn-on in current (sub-threshold slopes approaching 60 mV/decade, the second steepest value for OFETs reported so far), and decent uniformity in large areas. These characteristics are superior to the neat TIPS-PEN devices. Using channel scaling measurements and scanning Kelvin probe microscopy, the sharp turn-on in current in the blends was attributed to a contact (tunneling) barrier that originates from a thin insulating polystyrene layer between the injecting contacts and the semiconductor channel. These new insights on device operations of our blend transistors provide valuable guidelines towards next-generation organic transistors based on small-molecule semiconductor and insulating polymer blends. Following the knowledge gained in Chapter 3, and in line with the objective (iv) of this thesis on the fundamental understanding of device operation, a so-called ‘electric field confinement effect’ on charge transport in polycrystalline OFETs was presented in Chapter 4. It is known that the charge-carrier mobility in organic semiconductors is only weakly dependent on the electric field at low fields; our experimental charge-carrier mobility in OFETs using TIPS-PEN was found to be surprisingly field-dependent at low source-drain fields. Corroborated by scanning Kelvin probe measurements, we explained this experimental observation by the severe difference between the local lateral-field dependences within grains and at grain boundaries. Redistribution of accumulated charges creates very strong local lateral fields in the latter regions. These strong local fields in the grain boundaries result in the carrier mobility in grain boundaries to become field-dependent, and as the mobility in grain-boundaries limits the overall mobility its field-dependence translates to a field-dependence of the average mobility. We further confirmed this picture by verifying that the charge-carrier mobility in channels having no grain boundaries, made from the same type of organic semiconductor, is not significantly field-dependent. Finally, we showed that our model allows us to "quantitatively" describe the source-drain field dependence of mobility in polycrystalline OFETs. Then, we moved to using molecular design to control the morphology and molecular order of organic semiconductors. In Chapter 5 we presented a new TIPS-PEN derivative, namely BTE-TIPS-PEN, with ethyl substituents at the 2,3,9,10 backbone positions to modulate the solubility and film-forming properties. High-performance OFETs were readily fabricated using a single-step process without the need to form blends or the use of top-gate architecture. Average mobilities above 1 cm2/Vs were measured at low-operating voltages for specific crystal orientations, with the highest saturation mobility reaching as high as 3.92 cm2/Vs, confirming that an improved molecular design can indeed result in a controlled macro- and micro-structure of BTE-TIPS-PEN thin films that positively influences the electronic properties. The high device reproducibility obtained for BTE-TIPS-PEN is also promising for the technological exploitation of such discrete devices in large-area organic electronics. Next, we demonstrated in Chapter 6, that a careful selection of the casting temperature alone can allow a rapid production of OFETs with uniform and reproducible device performance over large areas. Based on a systematic investigation on the thermal behaviour of 5,11-bis(triethyl silylethynyl) anthradithiophene (TES ADT), we presented four distinctive solid-state phases of TES ADT exhibiting drastically different charge-transport properties, deduced from OFET device characteristics corroborated by Lateral Time-of-Flight (L-ToF) photoconductivity measurements. The best-performing crystal polymorph of TES ADT was identified: when casting solutions of TES ADT dissolved in chloroform at a substrate temperature of more than 20 °C below its glass transition temperature, highly-crystalline and homogeneous TES ADT thin films can be facilely produced in a single-step, without the need for any post-depositions as previously reported, opening pathways towards high-throughput and reliable fabrication of high-performance OFETs. In Chapter 7 we presented the first highly-reproducible n-type SAMFET, based on a perylene derivative (namely PBI-PA) with a phosphonic acid anchoring group which enables an efficient fixation to aluminum oxide. Simple device fabrication under ambient conditions leads to a complete surface coverage of the aluminum oxide with a monolayer of PBI-PA, and to transistors with electron mobilities up to 10-3 cm2/Vs for channel length as long as 100 µm. By implementing p- and n-type SAMFETs in one circuit, a complementary inverter based solely on SAMFETs, with a large noise margin of 7 volts and a gain up to 17, was demonstrated for the first time, paving the way to robust and low-power self-assembled monolayer based complementary circuits. As a side topic of this thesis, in the last Chapter, we introduced an unconventional use of the molecular (polymer chain/dipole) alignment, in the dielectric layer of organic field-effect transistors. Chapter 8 presented a voltage-programmable light-emitting field-effect transistor (LEFET) using a ferroelectric polymer as the gate dielectric. We showed by both experimental observations and numerical modeling that, when the ferroelectric gate dielectric is polarized in opposite directions at the drain and source sides of the channel, respectively, both electron and hole currents are enhanced, resulting in more charge recombination and ~ 10 times higher light emission in a ferroelectric LEFET, compared to the device with non-ferroelectric gate. As a result of the ferroelectric poling (dipole alignment), our ferroelectric LEFETs exhibit repeated programmability in light emission, and an external quantum efficiency (EQE) of up to 1.06 %. Numerical modeling revealed that the remnant polarization charge of the ferroelectric layer tends to ‘pin’ the position of the recombination zone, paving the way to integrate specific optical out-coupling structures in the channel of these devices to further increase the brightness. The results and new insights obtained in this thesis will serve as important guidelines for the development of new generation solution-processed organic transistors towards large-area organic (opto-) electronics

Indium-Gallium-Zinc Oxide Thin-Film Transistors for Active-Matrix Flat-Panel Displays

Amorphous oxide semiconductors (AOSs) including amorphous InGaZnO (a-IGZO) areexpected to be used as the thin-film semiconducting materials for TFTs in the next-generation ultra-high definition (UHD) active-matrix flat-panel displays (AM-FPDs). a-IGZO TFTs satisfy almost all the requirements for organic light-emitting-diode displays (OLEDs), large and fast liquid crystal displays (LCDs) as well as three-dimensional (3D) displays, which cannot be satisfied using conventional amorphous silicon (a-Si) or polysilicon (poly-Si) TFTs. In particular, a-IGZO TFTs satisfy two significant requirements of the backplane technology: high field-effect mobility and large-area uniformity.In this work, a robust process for fabrication of bottom-gate and top-gate a-IGZO TFTs is presented. An analytical drain current model for a-IGZO TFTs is proposed and its validation is demonstrated through experimental results. The instability mechanisms in a-IGZO TFTs under high current stress is investigated through low-frequency noise measurements. For the first time, the effect of engineered glass surface on the performance and reliability of bottom-gate a-IGZO TFTs is reported. The effect of source and drain metal contacts on electrical properties of a-IGZO TFTs including their effective channel lengths is studied. In particular, a-IGZO TFTs with Molybdenum versus Titanium source and drain electrodes are investigated. Finally, the potential of aluminum substrates for use in flexible display applications is demonstrated by fabrication of high performance a-IGZO TFTs on aluminum substrates and investigation of their stability under high current electrical stress as well as tensile and compressive strain

Circuit Design and Compact Modeling in Printed Electronics Based on Inorganic Materials

Die gedruckte Elektronik ist ein im Vergleich zur konventionellen Siliziumtechnologie junges Forschungsgebiet. Die Idee hinter der gedruckten Elektronik ist es elektronische Bauteile wie Widerstände, Kapazitäten, Solarzellen, Dioden und Transistoren mit gängigen Druckmethoden herzustellen. Dabei ist es möglich die elektronischen Bauteile auf unbiegsamen Substrate, wie Glas oder Silizium, als auch auf biegsamen Substrate, wie Papier und Folie, zu drucken. Aufgrund des Druckprozesses, sind die Herstellungskosten gering, da drucken ein additiver Prozess ist und somit teure Masken obsolet sind. In einem Feldeffekttransistor, wird der Halbleiter zwischen zwei Elektroden (Drain- und Source) gedruckt. Die Drain- und Source-Elektroden werden dabei durch einen Vakuum- oder Druckprozess abgeschieden und strukturiert. Der halbleitende Kanal wird durch einen Dielektrikum von der Gate-Elektrode isoliert. Auch für das Dielektrikum und die Gate-Elektrode sind ein Vakuum- oder Druckprozess denkbar. Standardmäßig finden organische Materialien Einsatz in der gedruckten Elektronik. Leider weisen organische Halbleiter, in einem Feldeffekttransistor, nur eine geringe Ladungsträgerbeweglichkeit ($\leq 1$ cm$^2$(Vs)$^{-1}$) auf. Die niedrige Ladungsträgerbeweglichkeit führt zu einer geringen Ladungsträgerdichte im Halbleiter und als Resultat zu geringen Stromdichten. Auch sind größtenteils nur p-leitende Halbleiter für den Einsatz in Schaltungen vorhanden, weswegen die meisten Schaltungen nur p-leitende Feldeffekttransistoren besitzen. Ein weiterer Nachteil der organischen Elektronik ist, dass die eingesetzten Dielektrika mit dem Halbleiter eine mangelhafte Grenzfläche bildet. Deshalb sind Versorgungsspannungen in Bereich von 5 V keine Seltenheit. Eine interessante Alternative zu organischen Halbleitern sind Materialien die der Kategorie der Oxide zugeordnet sind. Zum Beispiel in Indiumoxid (In$_{2}$O$_{3}$) ist eine Ladungsträerbeweglichkeit um die 100 cm$^2$(Vs)$^{-1}$ messbar. Leider sind durch Oxide realisierte p-leitende Feldeffekttransistoren sehr selten, weshalb die meisten Schaltungen auf n-leitenden Feldeffekttransistoren basieren. Ein weiterer Nachteil von Metalloxidhalbleitern is das hohe Glühtemperaturen (\sim 400 \, ^\circC) benötigt werden um die richtige Kristallstruktur zu erzielen. Durch den Einsatz eines Elektrolyten, anstatt eines Dielektrikum, werden die benötigten hohen Versorgungsspannungen auf 1 V reduziert. Der Grund für die Reduzierung der Versorgungsspannung liegt in der hohen Kapazität ($\sim 5 \, \mu$F(cm)$^{-1}$), die sich zwischen der Gate-Elektrode und dem Kanal ausbildet. Die optimale Grenzfläche zwischen der Gate-Elektrode und dem Elektrolyten sowie als auch zwischen dem Elektrolyten und dem Kanal, wo sich eine Helmholtz-Doppelschicht ausbildet, ist der Grund für die hohe Kapazität. In dieser Arbeit, werden die Vorteile der hohen Ladungsträgerbeweglichkeit, resultierend von einem Indiumoxid-Kanal, und der niedrigen Versorgungsspannungen, durch den Einsatz eines Elektrolyten als Isolator, in einem gedruckten Transistor kombiniert. Daher ist das Ziel zunächst Transistoren basierend auf einem Elektrolyten und Indiumoxid-Kanal zu charakterisieren und zu modellieren. Auch werden Möglichkeiten zum Schaltungsentwurf mit der hier vorgestellten Transistortechnologie ausgearbeitet. Der Schaltungsentwurf wird anhand mikroelektronischen Zellen und Ringoszillator-Strukturen verifiziert. Wichtig für den Schaltungsentwurf sind Modelle die fähig sind die elektrischen Eigenschaften eines Transistors abzubilden. Dabei muss die simulierte Kurve Stetigkeit und Kontinuität aufweisen um Konvergenzprobleme während der Simulation zu verhindern. Zur Modellierung der elektrischen Eigenschaften und Ströme der Transistoren wird ein Modell basierend auf den Curtice-Modell entwickelt. Der Bereich über der Schwellwertspannung wird daher durch das Curtice-Modell abgebildet und der Bereich unter der Schwellspannung durch ein aus Siliziumtransistoren bekanntes Standard-Modell beschrieben. Kontinuität und Stetigkeit wird durch eine Interpolation zwischen den beiden Transistormodellen gewährleistet. Ein Verglich zwischen gemessenen und simulierten Daten zeigt das das Modell die hier vorgestellte Transistortechnologie sehr gut abbilden kann. Das entwickelte Transistormodel wird zur unterstützung des Schaltungsentwurf in einem Prozesskit (PDK) integriert. Dadurch ist das Verhalten einer Schaltung durch Simulation vorhersehbar. In der Simulation können auch der Einfluss der Umwelt, z.B. Luftfeuchtigkeit, auf die Transistoren analysiert werden. In der digitalen Schaltungstechnik wird ein p-leitender Feldeffekttransistor verwendet um ein Eingangssignal hochzusetzen, während um ein Signal runterzusetzen, ein n-leitender Feldeffekttransistor von Vorteil ist. Da p-leitende Oxide selten und unzuverlässig sind, wird der p-leitende Feldeffekttransistor durch einen Widerstand (Transistor-Widerstand-Logik (TRL)) oder einen n-leitenden Feldeffekttransistor (Transistor-Transistor-Logik (TTL)) ersetzt. Ein Inverter in TRL weist bei einer Versorgungsspannung von 1 V einen Verstärkungsfaktor von ungefähr -5 auf und eine Signalverzögerung von 0.9 ms. Die Oszillatorfrequenz im entsprechend Ringoszillator beträgt 296 Hz. Weitere Logikgatter (NAND, NOR und XOR) sind ebenfalls realisierbar mit TRL-Entwürfe. In TTL wird der p-leitende Feldeffekttransistor durch einen n-leitenden Verarmungstyps Feldeffekttransistor ersetzt. Die in der TTL entworfene Logikgatter verhalten sich identisch zu den TTR-Zellen aber die Frequenz vom Ringoszillator steigt bis in den unteren kHz-Bereich an. In TTL ist es ebenfalls möglich die Verlustleistung um einen Faktor von 6 zu reduzieren