Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

By the continuing downscaling of sub-micron transistors in the range of few to one deca-nanometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10nm×10nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial “frozen noise”, which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the “frozen noise” contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of “innovation variance”, which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the “statistics behind the numbers”, because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law

Synthesis and analysis of nonlinear, analog, ultra low power, Bernoulli cell based CytoMimetic circuits for biocomputation

A novel class of analog BioElectronics is introduced for the systematic implementation of ultra-low power microelectronic circuits, able to compute nonlinear biological dynamics. This class of circuits is termed ``CytoMimetic Circuits'', in an attempt to highlight their actual function, which is mimicking biological responses, as observed experimentally. Inspired by the ingenious Bernoulli Cell Formalism (BCF), which was originally formulated for the modular synthesis and analysis of linear, time-invariant, high-dynamic range, logarithmic filters, a new, modified mathematical framework has been conceived, termed Nonlinear Bernoulli Cell Formalism (NBCF), which forms the core mathematical framework, characterising the operation of CytoMimetic circuits. The proposed nonlinear, transistor-level mathematical formulation exploits the striking similarities existing between the NBCF and coupled ordinary differential equations, typically appearing in models of naturally encountered biochemical systems. The resulting continuous-time, continuous-value, low-power CytoMimetic electronic circuits succeed in simulating with good accuracy cellular and molecular dynamics and found to be in very good agreement with their biological counterparts. They usually occupy an area of a fraction of a square millimetre, while consuming between hundreds of nanowatts and few tenths of microwatts of power. The systematic nature of the NBCF led to the transformation of a wide variety of biochemical reactions into nonlinear Log-domain circuits, which span a large area of different biological model types. Moreover, a detailed analysis of the robustness and performance of the proposed circuit class is also included in this thesis. The robustness examination has been conducted via post-layout simulations of an indicative CytoMimetic circuit and also by providing fabrication-related variability simulations, obtained by means of analog Monte Carlo statistical analysis for each one of the proposed circuit topologies. Furthermore, a detailed mathematical analysis that is carefully addressing the effect of process-parameters and MOSFET geometric properties upon subthreshold translinear circuits has been conducted for the fundamental translinear blocks, CytoMimetic topologies are comprised of. Finally, an interesting sub-category of Neuromorphic circuits, the ``Log-Domain Silicon Synapses'' is presented and representative circuits are thoroughly analysed by a novel, generalised BC operator framework. This leads to the conclusion that the BC operator consists the heart of such Log-domain circuits, therefore, allows the establishment of a general class of BC-based silicon synaptic circuits, which includes most of the synaptic circuits, implemented so far in Log-domain.Open Acces

Study and design of topologies and components for high power density DC-DC converters

Size reduction of low power electronic DC–DC converters is a topic of major interest for power electronics which requires the study and design of circuits and components working under redefined requirements. For this purpose, novel circuital topologies provide advantages in terms of power density increment, especially where a single chip design is feasible. These concepts have been applied to design and implement an integrated high step-down multiphase buck converter and to study the miniaturization of a stackable fiflyback architecture. Particular attention has been dedicated to power inductors, focusing on the modeling and measurement of magnetic materials’ hysteresis and core losses

Integrated Circuit Design for Hybrid Optoelectronic Interconnects

This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool. Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible. The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link power budgets for NRZ, PAM-4 and PAM-8 signaling modulations are simulated at system-level. The optimal transmitter extinction ratio (ER) is derived based on the required receiver\u27s minimum optical modulation amplitude (OMA). A limiting receiver is fabricated in the IBM 130 nm CMOS process. By side- by-side wire-bonding to a commercial high-speed InGaAs/InP PIN photodiode, we demonstrate that the hybrid optoelectronic limiting receiver can achieve the bit error rate (BER) of 10-12 with a -6.7 dBm sensitivity at 4 Gb/s. A full-rate, 4-channel 29-1 length parallel PRBS is fabricated in the IBM 130 nm SiGe BiCMOS process. Together with a 10 GHz phase locked loop (PLL) designed from system architecture to transistor level design, the PRBS is demonstrated operating at more than 10 Gb/s. Lessons learned from high-speed PCB design, dealing with signal integrity issue regarding to the PCB transmission line are summarized

High-voltage ESD structures and ESD protection concepts in smart power technologies

Electro-static discharge (ESD) event can cause upset or permanent damage of integrated circuits (IC) and electrical systems. The risk of ESD fails needs to be mitigated or prevented. ESD robustness of IC products and electrical systems is specified, verified and qualified according to respective ESD standards. For high-voltage IC products based on smart power semiconductor technologies for industrial, power and automotive applications, design of effective and cost-efficient ESD protection is a big challenge, demanding wide and deep technical knowledge throughout high-frequency and high-power characterization techniques, semiconductor device physic, circuit design as well as modeling and simulation. The required measurement setups and tester components are developed and introduced. The characterization of ESD protection devices, IC and off-chip circuit elements is enabled and improved. The rise-time filters are important for the study of rise-time dependent ESD robustness. The human metal model (HMM) tester as an alternative to IEC ESD generators provides voltage waveform measurement with good quality in addition to current waveform measurement. It can be used for wafer-level or package-level device characterization. The measurement results of HMM tester and IEC ESD generator are compared. The on-chip ESD protection design relies on proper choice of different types of ESD protection devices and structures, depending on ESD specifications and IC applications. Typical on-chip ESD protection, whether snapback or non-snapback, single device or ESD circuit is introduced. The failure levels studies give a systematic benchmark of the ESD protection devices and structures, concerning device area, clamping voltage and other relevant parameters. The trade-off between those parameters and limitation of different ESD protection is discussed. Moreover, understanding of ESD failure modes is the key to implement effective ESD design. A unique ESD failure mode of smart power semiconductor device is discovered and investigated in detail. In the scope of finding ESD solutions, new active ESD clamps have been further developed in this work. The study of ESD protection is extended to the system-level involving on- and off-chip ESD protection elements. The characteristics of typical off-chip elements as well as the interaction between IC and off-chip protection elements plays essential role on the system robustness. A system-level ESD simulation incorporating IC and off-chip protection elements is desired for system efficient ESD design (SEED). A behavioral ESD model is developed which reproduces pulse-energy-dependent failure levels and self-heating effects. This modeling methodology can be used for assessment of system robustness even beyond ESD time-domain. The validation of the models is given by representative application examples. Several main challenges of high-voltage ESD design in smart power technologies have been addressed in this work, which can serve as guidance for ESD development and product support in future power semiconductor technologies

Design of discrete time controllers for DC-DC boost converter

06.03.2018 tarihli ve 30352 sayılı Resmi Gazetede yayımlanan “Yükseköğretim Kanunu İle Bazı Kanun Ve Kanun Hükmünde Kararnamelerde Değişiklik Yapılması Hakkında Kanun” ile 18.06.2018 tarihli “Lisansüstü Tezlerin Elektronik Ortamda Toplanması, Düzenlenmesi ve Erişime Açılmasına İlişkin Yönerge” gereğince tam metin erişime açılmıştır.DC-DC dönüştürücüler sahip oldukları yüksek verim, yüksek güç yoğunluğu, yüksek güç seviyeleri, düşük maliyet ve küçük fiziksel yapı özelliklerinden dolayı modern güç elektroniği sistemlerinde yaygın olarak kullanılmaktadırlar. Genel olarak alçaltıcı, yükseltici ve alçaltıcı/yükseltici tipinde olabilen dönüştürücüler çoklu çıkış gerilimine sahip olabilmektedirler. Yükseltici dönüşürücüler, giriş geriliminden daha yüksek bir çıkış gerilimi üreten bir tür anahtarlamalı-modlu dc-dc dönüştürücülerdir. Yükseltici tip DC-DC dönüştürücünün ortalama durum-uzay tekniğine dayalı küçük-sinyal modeli elde edilmiştir. Ayrık-zaman kontrolör iki ayı yöntem, frekans domeni ve durum-uzay yöntemleri, kullanılarak tasarlanmıştır. Kök-yer eğrisi yöntemi ile integral kontrolör tasarlanmıştır. Durum geribesleme kazanç matrisi hem kutup yerleştirme hem de doğrusal optimal kuadratik regülatör yaklaşımları kullanılarak tasarlanmıştır. Kontrolcülü yükseltici dönüştürücünün performansı MATLAB/SIMULINK ortamında yapılan similasyon çalışmaları ile incelenmiş ve doğrulanmıştır. Tasarlanan kontrolör türleri tasarım metodolojisi, uygulama problemleri ve performans açısından karşılaştırılmıştır. Tasarlanan kontrol yöntemlerinin birbirine yakın bir performansa sahip olduğu gözlemlenmiştir. Bu çalışmada, yükseltici tip DC-DC dönüştürücüler için sürekli-hal ve dinamik karakteristik açısından uygun bir performansa sahip kontrolör tasarımı amaçlanmıştır.DC-DC converters are extensively used in modern power electronics devices due to their high efficiency, high power density, high power levels, low cost, and small size. In general, they can be step-up, step-down or step-up/down converters and can have multiple output voltages. Boost converter, (also known as a step-up converter) is a type of switched-mode dc-dc converter which produces output voltage that is greater than input voltage. A small signal modeling based on state space averaging technique for DC-DC Boost converter is carried out. Discrete time controller is designed using two design techniques; frequency domain and state space methods. Root locus technique is used to design an integral controller. A state feedback gain matrix is designed by pole placement technique and Linear Quadratic Optimal Regulator (LQR) methods. The performance of the controlled boost converter are investigated and verified through MATLAB/SIMULINK simulation. Comparison between the designed controllers related to the design methodology, implementation issues and performance is carried out. It is seen that the designed controllers yielded comparable performances. In this study, it is aimed to design a controller for DC-DC boost converter to provide satisfactory performance in term of static, dynamic and steady-state characteristics

Subwavelength Sensing Using Nonlinear Feedback in a Wave-Chaotic Cavity

<p>Typical imaging systems rely on the interactions of matter with electromagnetic radiation, which can lead to scattered waves that are radiated away from the imaging area. The goal such an imaging device is to collect these radiated waves and focus them onto a measurement detector that is sensitive to the wave's properties such as wavelength (or color) and intensity. The detector's measurements of the scattered fields are then used to reconstruct spatial information about the original matter such as its shape or location. However, when a scattered wave is collected by the imaging device, it diffracts and inteferes with itself. The resulting interference pattern can blur spatial information of the reconstructed image. This leads to a so-called diffraction limit, which describes the minimum sizes of spatial features on a scatterer that can be resolved using conventional imaging techniques. The diffraction limit scales with the wavelength &lambda; of the illuminating field, where the limit for conventional imaging with visible light is approximately 200 nm. Investigating subwavelength objects (< &lambda;) requires more advanced measurement techniques, and improving the resolving capabilities of imaging devices continues to be an active area of research.</p><p>Here, I describe a new sensing technique for resolving the position of a subwavelength scatterer (< &lambda;) with vastly subwavelength resolution (<< &lambda;). My approach combines two separate fields of scientific inquiry: time-delayed nonlinear feedback and wave chaos. In typical time-delayed nonlinear feedback systems, the output of a nonlinear device is delayed and fed back to its input. In my experiment, the output of a radio-frequency (&lambda; ~ 15 cm) nonlinear circuit is injected into a complex scattering environment known as a wave-chaotic cavity. Inside the cavity, the field interacts with a subwavelength dielectric object from all sides, and a portion of the scattered waves are coupled out of the cavity, amplified, and fed back to the input of the nonlinear circuit. The resulting closed-feedback loop generates its own radio-frequency illumination field (> 1 GHz), which contains multiple wavelengths and is sensitive to location of the scattering object. Using the dynamical changes in the illumination field, I demonstrate subwavelength position-sensing of the scatterer's location in the cavity with a one-dimensional resolution of ~&lambda;/10,000 and a two-dimensional resolution of ~ &lambda;/300. </p><p>This novel method demonstrates that the dynamical changes of a feedback oscillator can be exploited for resolving subwavelength spatial features. Unlike conventional imaging techniques, it uses a single scalar measurement of the scattered field and takes advantage of a complex scattering environment. Furthermore, this work demonstrates the first application of quasiperiodic dynamics (oscillations with incommensurate frequencies) from a nonlinear system. Using the key ingredients from my radio-frequency system, I extend my method to an experiment that uses optical frequencies (&lambda; = 1550 nm) to demonstrate subwavelength sensing in two dimensions with a resolution of approximately 10 nm. Because this new sensing technique can be adapted to multiple experiments over vastly different length scales, it represents a potential platform for creating a new class subwavelength imaging devices.</p>Dissertatio

Ultra low power circuits for a miniature apnoea detection device

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A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme

An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.Ph.D.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghu