Simulating CCDs for the Chandra Advanced CCD Imaging Spectrometer

We have implemented a Monte Carlo algorithm to model and predict the response of various kinds of CCDs to X-ray photons and minimally-ionizing particles and have applied this model to the CCDs in the Chandra X-ray Observatory's Advanced CCD Imaging Spectrometer. This algorithm draws on empirical results and predicts the response of all basic types of X-ray CCD devices. It relies on new solutions of the diffusion equation, including recombination, to predict the radial charge cloud distribution in field-free regions of CCDs. By adjusting the size of the charge clouds, we can reproduce the event grade distribution seen in calibration data. Using a model of the channel stops developed here and an insightful treatment of the insulating layer under the gate structure developed at MIT, we are able to reproduce all notable features in ACIS calibration spectra. The simulator is used to reproduce ground and flight calibration data from ACIS, thus confirming its fidelity. It can then be used for a variety of calibration tasks, such as generating spectral response matrices for spectral fitting of astrophysical sources, quantum efficiency estimation, and modeling of photon pile-up.Comment: 42 pages, 22 figures; accepted for publication in Nuclear Instruments and Methods in Physics Research, Section A; paper with high-quality figures can be found at ftp://ftp.astro.psu.edu/pub/townsley/simulator.p

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Electronic spin transport in graphene field effect transistors

Spin transport experiments in graphene, a single layer of carbon atoms, indicate spin relaxation times that are significantly shorter than the theoretical predictions. We investigate experimentally whether these short spin relaxation times are due to extrinsic factors, such as spin relaxation caused by low impedance contacts, enhanced spin flip processes at the device edges or the presence of an aluminium oxide layer on top of graphene in some samples. Lateral spin valve devices using a field effect transistor geometry allowed for the investigation of the spin relaxation as a function of the charge density, going continuously from metallic hole to electron conduction (charge densities of $n\sim 10^{12}$cm$^{-2}$) via the Dirac charge neutrality point ($n \sim 0$). The results are quantitatively described by a one dimensional spin diffusion model where the spin relaxation via the contacts is taken into account. Spin valve experiments for various injector/detector separations and spin precession experiments reveal that the longitudinal (T$_1$) and the transversal (T$_2$) relaxation times are similar. The anisotropy of the spin relaxation times $\tau_\parallel$ and $\tau_\perp$, when the spins are injected parallel or perpendicular to the graphene plane, indicates that the effective spin orbit fields do not lie exclusively in the two dimensional graphene plane. Furthermore, the proportionality between the spin relaxation time and the momentum relaxation time indicates that the spin relaxation mechanism is of the Elliott-Yafet type. For carrier mobilities of 2-5$\times 10^3$ cm2^/Vs and for graphene flakes of 0.1-2 $\mu$m in width, we found spin relaxation times of the order of 50-200 ps, times which appear not to be determined by the extrinsic factors mentioned above.Comment: 11 pages, 13 figure

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

Impact of parameter variations on circuits and microarchitecture

Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits. This article presents an overview of the main sources of variability and surveys variation-tolerant circuit and microarchitectural approaches.Peer ReviewedPostprint (published version

Single-Electron Traps: A Quantitative Comparison of Theory and Experiment

We have carried out a coordinated experimental and theoretical study of single-electron traps based on submicron aluminum islands and aluminum oxide tunnel junctions. The results of geometrical modeling using a modified version of MIT's FastCap were used as input data for the general-purpose single-electron circuit simulator MOSES. The analysis indicates reasonable quantitative agreement between theory and experiment for those trap characteristics which are not affected by random offset charges. The observed differences between theory and experiment (ranging from a few to fifty percent) can be readily explained by the uncertainty in the exact geometry of the experimental nanostructures.Comment: 17 pages, 21 figures, RevTex, eps

Diffusive Transport in Quasi-2D and Quasi-1D Electron Systems

Quantum-confined semiconductor structures are the cornerstone of modern-day electronics. Spatial confinement in these structures leads to formation of discrete low-dimensional subbands. At room temperature, carriers transfer among different states due to efficient scattering with phonons, charged impurities, surface roughness and other electrons, so transport is scattering-limited (diffusive) and well described by the Boltzmann transport equation. In this review, we present the theoretical framework used for the description and simulation of diffusive electron transport in quasi-two-dimensional and quasi-one-dimensional semiconductor structures. Transport in silicon MOSFETs and nanowires is presented in detail.Comment: Review article, to appear in Journal of Computational and Theoretical Nanoscienc

Single Particle Transport in Two-dimensional Heterojunction Interlayer Tunneling Field Effect Transistor

The single particle tunneling in a vertical stack consisting of monolayers of two-dimensional semiconductors is studied theoretically and its application to a novel Two-dimensional Heterojunction Interlayer Tunneling Field Effect Transistor (Thin-TFET) is proposed and described. The tunneling current is calculated by using a formalism based on the Bardeen's transfer Hamiltonian, and including a semi-classical treatment of scattering and energy broadening effects. The misalignment between the two 2D materials is also studied and found to influence the magnitude of the tunneling current, but have a modest impact on its gate voltage dependence. Our simulation results suggest that the Thin-TFETs can achieve very steep subthreshold swing, whose lower limit is ultimately set by the band tails in the energy gaps of the 2D materials produced by energy broadening. The Thin-TFET is thus very promising as a low voltage, low energy solid state electronic switch