An advanced Framework for efficient IC optimization based on analytical models engine

En base als reptes sorgits a conseqüència de l'escalat de la tecnologia, la present tesis desenvolupa i analitza un conjunt d'eines orientades a avaluar la sensibilitat a la propagació d'esdeveniments SET en circuits microelectrònics. S'han proposant varies mètriques de propagació de SETs considerant l'impacto dels emmascaraments lògic, elèctric i combinat lògic-elèctric. Aquestes mètriques proporcionen una via d'anàlisi per quantificar tant les regions més susceptibles a propagar SETs com les sortides més susceptibles de rebre'ls. S'ha desenvolupat un conjunt d'algorismes de cerca de camins sensibilitzables altament adaptables a múltiples aplicacions, un sistema lògic especific i diverses tècniques de simplificació de circuits. S'ha demostrat que el retard d'un camí donat depèn dels vectors de sensibilització aplicats a les portes que formen part del mateix, essent aquesta variació de retard comparable a la atribuïble a les variacions paramètriques del proces.En base a los desafíos surgidos a consecuencia del escalado de la tecnología, la presente tesis desarrolla y analiza un conjunto de herramientas orientadas a evaluar la sensibilidad a la propagación de eventos SET en circuitos microelectrónicos. Se han propuesto varias métricas de propagación de SETs considerando el impacto de los enmascaramientos lógico, eléctrico y combinado lógico-eléctrico. Estas métricas proporcionan una vía de análisis para cuantificar tanto las regiones más susceptibles a propagar eventos SET como las salidas más susceptibles a recibirlos. Ha sido desarrollado un conjunto de algoritmos de búsqueda de caminos sensibilizables altamente adaptables a múltiples aplicaciones, un sistema lógico especifico y diversas técnicas de simplificación de circuitos. Se ha demostrado que el retardo de un camino dado depende de los vectores de sensibilización aplicados a las puertas que forman parte del mismo, siendo esta variación de retardo comparable a la atribuible a las variaciones paramétricas del proceso.Based on the challenges arising as a result of technology scaling, this thesis develops and evaluates a complete framework for SET propagation sensitivity. The framework comprises a number of processing tools capable of handling circuits with high complexity in an efficient way. Various SET propagation metrics have been proposed considering the impact of logic, electric and combined logic-electric masking. Such metrics provide a valuable vehicle to grade either in-circuit regions being more susceptible of propagating SETs toward the circuit outputs or circuit outputs more susceptible to produce SET. A quite efficient and customizable true path finding algorithm with a specific logic system has been constructed and its efficacy demonstrated on large benchmark circuits. It has been shown that the delay of a path depends on the sensitization vectors applied to the gates within the path. In some cases, this variation is comparable to the one caused by process parameters variation

Doctor of Philosophy

dissertationThis thesis presents the design, fabrication and characterization of a microelectromechanical system (MEMS) based complete wireless microsystem for brain interfacing, with very high quality factor and low power consumption. Components of the neuron sensing system include TiW fixed-fixed bridge resonator, MEMS oscillator based action-potential-to-RF module, and high-efficiency RF coil link for power and data transmissions. First, TiW fixed-fixed bridge resonator on glass substrate was fabricated and characterized, with resonance frequency of 100 - 500 kHz, and a quality factor up to 2,000 inside 10 mT vacuum. The effect of surface conditions on resonator's quality factor was studied with 10s of nm Al2O3 layer deposition with ALD (atomic layer deposition). It was found that MEMS resonator's quality factor decreased with increasing surface roughness. Second, action-potential-to-RF module was realized with MEMS oscillator based on TiW bridge resonator. Oscillation signal with frequency of 442 kHz and phase noise of -84.75 dBc/Hz at 1 kHz offset was obtained. DC biasing of the MEMS oscillator was modulated with neural signal so that the output RF waveform carries the neural signal information. Third, high-efficiency RF coil link for power and data communications was designed and realized. Based on the coupled mode theory (CMT), intermediate resonance coil was introduced and increased voltage transfer efficiency by up to 5 times. Finally, a complete neural interfacing system was demonstrated with board-level integration. The system consists of both internal and external systems, with wireless powering, wireless data transfer, artificial neuron signal generation, neural signal modulation and demodulation, and computer interface displaying restored neuron signal

Techniques de routage pseudo-aléatoire pour une application micro-électronique

Résumé La problématique de routage est très actuelle. On en trouve des applications dans les GPS, les prévisions de trafic routier, mais aussi pour le prototypage sur FPGA, la fabrication de puces électroniques ou le trafic TCP/IP sur Internet. On trouve des publications sur le sujet depuis plusieurs dizaines d'années, mais on observe actuellement une recrudescence confirmant l'actualité, l'importance et la complexité de ce problème. Cette thèse concerne le routage et ses ressources pour une application dans un nouveau type de système micro-électronique, nommé le WaferBoardTM . Son noyau consiste en un circuit électronique intégré à l'échelle d'une tranche de silicium (wafer). Peu d'applications commerciales de la micro-électronique ont exploité ce niveau d'intégration. Ce système de prototypage rapide vise à réduire d'un ou deux ordres de grandeur le temps de développement de systèmes électroniques. Il nécessite un ensemble d'outils logiciel de support, dont un outil de routage très rapide, capable de produire des solutions valables en des temps de l'ordre de la minute, et de certaines fonctionnalités spécifiques, l'équilibrage de délai ou le reroutage à la volée, au sein d'une netlist déjà routée. La problématique de routage pour cette application peut être imagée comme suit. Étant donné un réseau routier régulier (les routes d’Amériques du Nord en version cartésienne par exemple) et 100,000 voitures au départ lundi à 8h a.m. dans tout le pays avec des sources et destinations très variées; calculer les chemins pour toutes les voitures de telle sorte qu'aucune ne prenne la même route dans la journée. Il est 7h59 a.m, vous avez 1 minute, et des ponts sont inaccessibles pour travaux, en voici la liste. Cet exemple simpliste donne une idée des ordres de grandeurs de la problématique de routage que l'on cherche à résoudre pour cette application. Un algorithme de routage prend en paramètres deux structures de données : un graphe (ou réseau d'interconnexions) constitué de n\oe{}uds (sommets) et d'arcsUn arc relie deux sommets du graphe, et une netlistDans ce contexte, un netlist réfère à une liste d'interconnexions entre composants, liste de n\oe{}uds électriques dont les points de départ et d'arrivée sont positionnés géographiquement. Ainsi, au lieu de voitures, il s'agit de router des signaux électriques dont les points de départ et d'arrivée sont dictés par la position des broches des composants placés sur le système de prototypage. Un réseau régulier maillé mufti-dimensionnel (plus généralement appelé « réseau d'interconnexions ») sert de réseau routier dont certaines routes sont défectueuses, des ponts inaccessibles. En effet, le réseau d'interconnexions est un circuit électronique intégré à l'échelle d'une tranche de silicium complète, ce qui implique la présence de défectuosités au sein de chaque circuit fabriqué. Contrairement aux circuits électroniques classiques, où chacun est testé et les défectueux écartés, une intégration à l'échelle de la tranche demande de fortes redondances au sein du circuit pour minimiser le taux de rejets. Pour l'application du WaferBoard, un certain nombre d'éléments du réseau d'interconnexions seront fort probablement défectueux sur chaque circuit produit; l'algorithme de routage se doit de prendre en compte ces éléments très particuliers. Cette contrainte ne se retrouve pas dans les applications plus classiques des routeurs que l'on retrouve dans les PCB, circuits FPGA ou circuits VLSI. D'autres contraintes s'appliquent à ce projet particulier : la latence induite par la technologie est environ un ordre de grandeur plus importante que celle dans les circuits sur PCB, ce qui impose un routage orienté vers sa réduction.----------Abstract The routing problem is very actual. Applications are found in GPS, road traffic forecast, but also for prototyping on FPGA, or TCP/IP traffic on the Internet. Publications on the subject have existed for several decades, but new publications keep appearing, confirming the importance and complexity of the problem. This thesis deals with routing and the resources it requires for a new category of micro-electronic applications, called the WaferBoard. It is an electronic circuit integrated at the wafer scale. Few commercial applications of micro-electronics have exploited this level of integration. This rapid prototyping system aims at reducing by one or two orders of magnitude the development time of digital circuits. It requires a very fast routing tool, capable of producing viable solutions in a few minutes, with dedicated functionality such as balancing delays and rerouting on the fly parts of a netlist. The routing problem for this application can be pictured as follows. Given a regular road network of the size of north america, if 100.000 cars were to start Monday 8 a.m. across the continent with a wide variety of sources and destinations; the challenge is to compute paths for all cars so none of them take the same route that day. It is 7:59 am, you have 1 minute, and some bridges are under road work: here is the list. This simplistic example gives an idea of the orders of magnitude of the problem that need to be solved for this application. A routing algorithm takes as input: a graph (or interconnection network) made of nodes and edges, and a netlst, a list of electrical nodes with starting and ending points physically placed. Therefore, instead of cars, the problem consists of routing electrical signals with points of departure and arrival dictated by the pin position of components placed on the prototyping system. A regular, multi-dimensional mesh (also called "interconnection network") serves as a road network, which contains defective roads and inaccessible bridges. Indeed, the interconnection network is an electronic circuit integrated across a full wafer, implying the presence of defects within each manufactured circuit. Unlike conventional electronic circuits, where each is tested and defective ones are set apart, wafer scale integrated applications require lots of redundancy in the circuit to minimize the rejection rate. In the WaferBoard, a number of elements of the interconnection network will be defective in each circuit; the routing algorithm must take into account these very specific elements. This constraint is not found in the classic applications of routers found in PCB, FPGA or VLSI circuits. Other restrictions apply to this particular project: the latency induced by the technology is about one order of magnitude greater than that in the circuits of PCBs, which requires a routing oriented towards computation time reduction. This constraint partly explains the network architecture used. Within the WaferIC, the shortest distance is not necessarily the one that offers the smallest latency. This property of the network complexifies the routing problem. Balancing delays within a group of arbitrary size nets is a necessary feature of the routing algorithm, and the difficulty is amplified by the computation time limit. Indeed, the interest of the application is to reduce the time for a user to test a circuit: the time of setup is extremely short, and estimated at a few minutes only

Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. By refiningthe fabrication techniques, using a self-aligned gate-last process, scaled10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabledby greatly improved p-type MOSFET performance reaching a maximumtransconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipationfor CMOS circuits requires good threshold voltage VT matching of the n- andp-type device, which is also demonstrated for basic inverter circuits. Thevarious effects contributing to VT-shifts are also studied in detail focusing onthe InAs channel devices (with highest transconductance of 2.6 mA/μm), byusing Electron Holography and a novel gate position variation method (PaperV).The advancements in all-III-V CMOS integration spawned individual studiesinto the strengths of the n- and p-type III-V devices, respectively. Traditionallymaterials such as InAs and InGaAs provide excellent electrontransport properties, therefore they are frequently used in devices for highfrequency RF applications. In contrast, the III-V p-type alternatives have beenlacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFETchannel, was designed and enabled by new manufacturing techniques, whichallowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs(Paper III). The new fabrication method allowed for integration of deviceswith symmetrical contacts as compared to previous work which relied on atunnel-contact at the source-side. By modelling based on measured data fieldeffecthole mobility of 70 cm2/Vs was calculated, well in line with previouslyreported studies on GaSb nanowires. The oxidation properties of the GaSbgate-stack was further characterized by XPS, where high intensities of xraysare achieved using a synchrotron source allowed for characterization ofnanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPSmeasurements, enabled a study of the time-dependence during full removalof GaSb native oxides.The last focus of the thesis was building on the existing strengths of verticalheterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,these devices demonstrate high-current densities (gm >3 mS/μm) and excellentmodulation properties (off-state current down to 1 nA/μm). However,minimizing the parasitic capacitances, due to various overlaps originatingfrom a low access-resistance design, has proven difficult. Therefore, newmethods for spacers in both the vertical and planar directions was developedand studied in detail. The new fabrication methods including sidewall spacersachieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which isthe established limit by optimized high-speed devices. The vertical spacertechnology, using SiO2 on the nanowire sidewalls, is further improved inthis thesis which enables new co-integration schemes for memory arrays.Namely, the refined sidewall spacer method is used to realize selective recessetching of the channel and reduced capacitance for large array memoryselector devices (InAs channel) vertically integrated with Resistive RandomAccess Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-memristor (1T1R) demonstrator cell shows excellent endurance and retentionfor the RRAM by maintaining constant ratio of the high and low resistive state(HRS/LRS) after 106 switching cycles

Energy-Efficient and Reliable Computing in Dark Silicon Era

Dark silicon denotes the phenomenon that, due to thermal and power constraints, the fraction of transistors that can operate at full frequency is decreasing in each technology generation. Moore’s law and Dennard scaling had been backed and coupled appropriately for five decades to bring commensurate exponential performance via single core and later muti-core design. However, recalculating Dennard scaling for recent small technology sizes shows that current ongoing multi-core growth is demanding exponential thermal design power to achieve linear performance increase. This process hits a power wall where raises the amount of dark or dim silicon on future multi/many-core chips more and more. Furthermore, from another perspective, by increasing the number of transistors on the area of a single chip and susceptibility to internal defects alongside aging phenomena, which also is exacerbated by high chip thermal density, monitoring and managing the chip reliability before and after its activation is becoming a necessity. The proposed approaches and experimental investigations in this thesis focus on two main tracks: 1) power awareness and 2) reliability awareness in dark silicon era, where later these two tracks will combine together. In the first track, the main goal is to increase the level of returns in terms of main important features in chip design, such as performance and throughput, while maximum power limit is honored. In fact, we show that by managing the power while having dark silicon, all the traditional benefits that could be achieved by proceeding in Moore’s law can be also achieved in the dark silicon era, however, with a lower amount. Via the track of reliability awareness in dark silicon era, we show that dark silicon can be considered as an opportunity to be exploited for different instances of benefits, namely life-time increase and online testing. We discuss how dark silicon can be exploited to guarantee the system lifetime to be above a certain target value and, furthermore, how dark silicon can be exploited to apply low cost non-intrusive online testing on the cores. After the demonstration of power and reliability awareness while having dark silicon, two approaches will be discussed as the case study where the power and reliability awareness are combined together. The first approach demonstrates how chip reliability can be used as a supplementary metric for power-reliability management. While the second approach provides a trade-off between workload performance and system reliability by simultaneously honoring the given power budget and target reliability

The Journal of Microelectronic Research

https://scholarworks.rit.edu/meec_archive/1015/thumbnail.jp

Developing Organic Electrochemical Electronics from Fundamentals to Integrated Circuit Components

Heutzutage werden riesige Datenmengen zwischen Endgeräten und Cloud-Servern verschoben. Cloud-Computing war nach Bloomberg bereits für 1% des weltweiten Stromverbrauchs im Jahr 2021 verantwortlich. Darüber hinaus kann die monopolartige Speicherung personenbezogener Daten schwerwiegende Auswirkungen auf die Gesellschaften unserer Welt haben. Um persönlichen Datenschutz und einen nachhaltigen Energieverbrauch zu gewährleisten, bedarf es einer Datenverarbeitung direkt am Endgerät; bezeichnet als Edge Computing. In diesem Zuge wird die Nachfrage nach individuell gestalteten Edge-Geräten rapide ansteigen. Der neu entstehende Markt bietet der organischen elektrochemischen Elektronik eine große Chance, vor allem für bioelektronische Anwendungen; allerdings muss die Chipintegration verbessert werden. In dieser Arbeit habe ich elektrochemische organische Elektronik für die Integration in Computersysteme untersucht. Insbesondere habe ich einen festen, photostrukturierbaren Elektrolyten entwickelt, der die Integration von OECTs ohne Kreuzkommunikation zwischen Bauteilen ermöglicht. Die OECTs arbeiten bei Spannungen unter 1V und schalten mit einem großen An/Aus-Verhältnis von 5 Größenordnungen und einer Unterschwellenschwingung nahe des thermodynamischen Minimums von 60mV/Dekade. Darüber hinaus wurden bei der Untersuchung der Hysterese des Bauelements drei verschiedene Hystereseregime identifiziert. Anschließend untersuchte ich die Schaltdynamik des OECTs und demonstrierte ein Top-Gate-OECT mit einer maximalen Betriebsfrequenz von 1 kHz. Beim Versuch, die komplexe Wechselwirkung zwischen Ionen und Elektronen in integrierten OECTs zu verstehen, habe ich einen grundlegenden elektrochemischen Mechanismus identifiziert. Die Abhängigkeit dieses Mechanismus’ von der Gate-Größe und der Drain-Überlapplänge wurde aufgezeigt und dieses Wissen zur Optimierung elektrochemischer Inverter genutzt. Zur Darstellung von OECT-basierten Schaltungskomponenten habe ich verschiedene Halbleiter verwendet und entsprechende Inverter hergestellt. Schließlich wurde die Hysterese eines einzigen ambipolaren Inverters zur Demonstration eines dynamischen Klinkenschalters genutzt. Im Rahmen dieser Arbeit habe ich die OECT-Technologie von den Anfängen bis hin zu integrierten Schaltkreiskomponenten entwickelt. Ich glaube, dass diese Arbeit ein Startschuss für Wissenschaftler und Ingenieure sein wird, um die OECT-Technologie in der realen Welt des Edge Computing einzusetzen.Nowadays, vast amounts of data are shuttled between end-user devices and cloud servers. This cloud computing paradigm was, according to Bloomberg, already responsible for 1% of the world’s electricity usage in 2021. Moreover, the monopoly-like storage of personal data can have a severe impact on the world’s societies. To guarantee data privacy and sustainable energy consumption in future, data computation directly at the end-user site is mandatory. This computing paradigm is called edge computing. Owing to the vast amount of end-user-specific applications, the demand for individually designed edge devices will rapidly increase. In this newly approaching market, organic electrochemical electronics offer a great opportunity, especially for bioelectronic applications; however, the integration into low-power-consuming systems has to be improved. In this work, I investigated electrochemical organic electronics for their integration into computational systems. In particular, I developed a solid photopatternable electrolyte that allows integrating organic electrochemical transistors (OECTs) without cross-talk between adjacent devices. The OECTs operate at voltages below 1 V, and exhibit a large on/off ratio of 5 orders of magnitude and a subthreshold-swing close to the thermodynamic minimum of 60mV/dec. Moreover, investigating the device’s hysteresis, three distinct hysteresis regimes were identified; the RC-time-dominated regime I, the retention time governed regime II, and the time-independent stable regime III. I then examined the OECT’s switching dynamics and, subsequently, demonstrated a top-gate device with a maximum operating frequency of 1 kHz. Trying to understand the complex interaction between ions and electrons in integrated OECTs, I disclosed a fundamental electrochemical mechanism and named it the electrochemical electrode coupling (EEC). The EEC’s dependence on gate size and drain overlap length was rigorously shown, and this knowledge was used to optimize electrochemical inverters. Yet, to exemplify OECT-based circuit components, I employed various semiconductors and fabricated five inverters, each with its unique advantage. Finally, the ambipolar inverter’s hysteresis was used to demonstrate a single-device dynamic latch, a basic in-memory computational element. In this thesis, I developed the OECT technology from an infancy stage to integrated circuit components. I believe that this work will be a starting signal for scientists and engineers to bring the OECT technology into real-world edge computing

Organic Photodiodes and Their Optoelectronic Applications

Recently, organic photodiodes (OPDs) have been acknowledged as a next-generation device for photovoltaic and image sensor applications due to their advantages of large area process, light weight, mechanical flexibility, and excellent photoresponse. This dissertation targets for the development and understanding of high performance organic photodiodes for their medical and industrial applications for the next-generation. As the first research focus, A dielectric / metal / dielectric (DMD) transparent electrode is proposed for the top-illumination OPDs. The fabricated DMD transparent electrode showed the maximum optical transmittance of 85.7 % with sheet resistance of 6.2 ohm/sq. In the second part of the thesis, a development of novel transfer process which enables the dark current suppression for the inverted OPD devices will be discussed. Through the effort, we demonstrated OPD with high D* of 4.82 x 10^12 Jones at reverse bias of 1.5 V with dark current density (Jdark) of 7.7 nA/cm2 and external quantum efficiency (EQE) of 60 %. Additionally in the third part, we investigate a high performance low-bandgap polymer OPD with broadband spectrum. By utilizing the novel transfer process to introduce charge blocking layers, significant suppression of the dark current is achieved while high EQE of the device is preserved. A low Jdark of 5 nA/cm2 at reverse bias of 0.5 V was achieved resulting in the highest D* of 1.5 x 10^13 Jones. To investigate the benefit for the various OPD applications, we developed a novel 3D printing technique to fabricate OPD on hemispherical concave substrate. The techniques allowed the direct patterning of the OPD devices on hemispherical substrates without excessive strain or deformation. Lastly, a simulation of the OPD stacked a-ITZO TFT active pixel sensor (APS) pixel with external transimpedance amplifier (TIA) readout circuit was performed.PHDElectrical & Computer Eng PhDUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137168/1/hyunskim_1.pd