Statistical strategies to capture correlation between overshooting effect and propagation delay time in nano-CMOS inverters

In this paper, we model statistical correlation between overshooting effect and propagation delay time in nano-CMOS technology considering the influence of intrinsic parameter fluctuations caused by discreteness of charge and granularity of matter. The impact of input slew rate, output capacitive load, and supply voltage on this statistical correlation is comprehensively studied. Moreover, we propose two alternative approaches which are capable of reproducing the statistical correlation as well as mean and standard deviation of both propagation delay time and overshoot voltage. We evaluate the accuracy of these alternative approaches against accurate Monte-Carlo simulations. It is shown that the statistical correlations are almost preserved using these alternative approaches

An advanced Framework for efficient IC optimization based on analytical models engine

En base als reptes sorgits a conseqüència de l'escalat de la tecnologia, la present tesis desenvolupa i analitza un conjunt d'eines orientades a avaluar la sensibilitat a la propagació d'esdeveniments SET en circuits microelectrònics. S'han proposant varies mètriques de propagació de SETs considerant l'impacto dels emmascaraments lògic, elèctric i combinat lògic-elèctric. Aquestes mètriques proporcionen una via d'anàlisi per quantificar tant les regions més susceptibles a propagar SETs com les sortides més susceptibles de rebre'ls. S'ha desenvolupat un conjunt d'algorismes de cerca de camins sensibilitzables altament adaptables a múltiples aplicacions, un sistema lògic especific i diverses tècniques de simplificació de circuits. S'ha demostrat que el retard d'un camí donat depèn dels vectors de sensibilització aplicats a les portes que formen part del mateix, essent aquesta variació de retard comparable a la atribuïble a les variacions paramètriques del proces.En base a los desafíos surgidos a consecuencia del escalado de la tecnología, la presente tesis desarrolla y analiza un conjunto de herramientas orientadas a evaluar la sensibilidad a la propagación de eventos SET en circuitos microelectrónicos. Se han propuesto varias métricas de propagación de SETs considerando el impacto de los enmascaramientos lógico, eléctrico y combinado lógico-eléctrico. Estas métricas proporcionan una vía de análisis para cuantificar tanto las regiones más susceptibles a propagar eventos SET como las salidas más susceptibles a recibirlos. Ha sido desarrollado un conjunto de algoritmos de búsqueda de caminos sensibilizables altamente adaptables a múltiples aplicaciones, un sistema lógico especifico y diversas técnicas de simplificación de circuitos. Se ha demostrado que el retardo de un camino dado depende de los vectores de sensibilización aplicados a las puertas que forman parte del mismo, siendo esta variación de retardo comparable a la atribuible a las variaciones paramétricas del proceso.Based on the challenges arising as a result of technology scaling, this thesis develops and evaluates a complete framework for SET propagation sensitivity. The framework comprises a number of processing tools capable of handling circuits with high complexity in an efficient way. Various SET propagation metrics have been proposed considering the impact of logic, electric and combined logic-electric masking. Such metrics provide a valuable vehicle to grade either in-circuit regions being more susceptible of propagating SETs toward the circuit outputs or circuit outputs more susceptible to produce SET. A quite efficient and customizable true path finding algorithm with a specific logic system has been constructed and its efficacy demonstrated on large benchmark circuits. It has been shown that the delay of a path depends on the sensitization vectors applied to the gates within the path. In some cases, this variation is comparable to the one caused by process parameters variation

DEEP SUBMICRON CMOS VLSI CIRCUIT RELIABILITY MODELING, SIMULATION AND DESIGN

CMOS VLSI circuit reliability modeling and simulation have attracted intense research interest in the last two decades, and as a result almost all IC Design For Reliability (DFR) tools now try to incrementally simulate device wearout mechanisms in iterative ways. These DFR tools are capable of accurately characterizing the device wearout process and predicting its impact on circuit performance. Nevertheless, excessive simulation time and tedious parameter testing process often limit popularity of these tools in product design and fabrication. This work develops a new SPICE reliability simulation method that shifts the focus of reliability analysis from device wearout to circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models are proposed for the most common MOSFET intrinsic wearout mechanisms, including Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), and Negative Bias Temperature Instability (NBTI). The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current waveforms. Then corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, SPICE simulation is performed again to check circuit functionality and analyze the impact of device wearout on circuit operation. Device wearout effects are lumped into a very limited number of failure equivalent circuit model parameters, and circuit performance degradation and functionality are determined by the magnitude of these parameters. In this new method, it is unnecessary to perform a large number of small-step SPICE simulation iterations. Therefore, simulation time is obviously shortened in comparison to other tools. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE model parameters, need to be accurately characterized at each interim wearout process. Thus device testing and parameter extraction work are also significantly simplified. These advantages will allow circuit designers to perform quick and efficient circuit reliability analyses and to develop practical guidelines for reliable electronic designs

Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. By refiningthe fabrication techniques, using a self-aligned gate-last process, scaled10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabledby greatly improved p-type MOSFET performance reaching a maximumtransconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipationfor CMOS circuits requires good threshold voltage VT matching of the n- andp-type device, which is also demonstrated for basic inverter circuits. Thevarious effects contributing to VT-shifts are also studied in detail focusing onthe InAs channel devices (with highest transconductance of 2.6 mA/μm), byusing Electron Holography and a novel gate position variation method (PaperV).The advancements in all-III-V CMOS integration spawned individual studiesinto the strengths of the n- and p-type III-V devices, respectively. Traditionallymaterials such as InAs and InGaAs provide excellent electrontransport properties, therefore they are frequently used in devices for highfrequency RF applications. In contrast, the III-V p-type alternatives have beenlacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFETchannel, was designed and enabled by new manufacturing techniques, whichallowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs(Paper III). The new fabrication method allowed for integration of deviceswith symmetrical contacts as compared to previous work which relied on atunnel-contact at the source-side. By modelling based on measured data fieldeffecthole mobility of 70 cm2/Vs was calculated, well in line with previouslyreported studies on GaSb nanowires. The oxidation properties of the GaSbgate-stack was further characterized by XPS, where high intensities of xraysare achieved using a synchrotron source allowed for characterization ofnanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPSmeasurements, enabled a study of the time-dependence during full removalof GaSb native oxides.The last focus of the thesis was building on the existing strengths of verticalheterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,these devices demonstrate high-current densities (gm >3 mS/μm) and excellentmodulation properties (off-state current down to 1 nA/μm). However,minimizing the parasitic capacitances, due to various overlaps originatingfrom a low access-resistance design, has proven difficult. Therefore, newmethods for spacers in both the vertical and planar directions was developedand studied in detail. The new fabrication methods including sidewall spacersachieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which isthe established limit by optimized high-speed devices. The vertical spacertechnology, using SiO2 on the nanowire sidewalls, is further improved inthis thesis which enables new co-integration schemes for memory arrays.Namely, the refined sidewall spacer method is used to realize selective recessetching of the channel and reduced capacitance for large array memoryselector devices (InAs channel) vertically integrated with Resistive RandomAccess Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-memristor (1T1R) demonstrator cell shows excellent endurance and retentionfor the RRAM by maintaining constant ratio of the high and low resistive state(HRS/LRS) after 106 switching cycles

Straintronics: A Leap towards Ultimate Energy Efficiency of Magnetic Memory and Logic

After decades of exponential growth of the semiconductor industries, predicted by Moore’s Law, the complementary metal-oxide semiconductor (CMOS) circuits are approaching their end of the road, as the feature sizes reach sub-10nm regimes, leaving electrical engineers with a profusion of design challenges in terms of energy limitations and power density. The latter has left the road for alternative technologies wide open to help CMOS overcome the present challenges. Magnetic random access memories (MRAM) are one of the candidates to assist with aforesaid obstacles. Proposed in the early 90’s, MRAM has been under research and development for decades. The expedition for energy efficient MRAM is carried out by the fact that magnetic logic, potentially, has orders of magnitude lower switching energy compared to a charge-based CMOS logic since, in a nanomagnet, magnetic domains would self-align with each other. Regrettably, conventional methods for switching the state of the cell in an MRAM, field induced magnetization switching (FIMS) and spin transfer torque (STT), use electric current (flow of charges) to switch the state of the magnet, nullifying the energy advantage, stated above. In order to maximize the energy efficiency, the amount of charge required to switch the state of the MTJ should be minimized. To this end, straintronics, as an alternative energy efficient method to FIMS and STT to switch the state of a nanomagnet, is proposed recently. The method states that by combining piezoelectricity and inverse magnetostriction, the magnetization state of the device can flip, within few nano-seconds while reducing the switching energy by orders of magnitude compared to STT and FIMS. This research focuses on analysis, design, modeling, and applications of straintronics-based MTJ. The first goal is to perform an in-depth analysis on the static and dynamic behavior of the device. Next, we are aiming to increase the accuracy of the model by including the effect of temperature and thermal noise on the device’s behavior. The goal of performing such analysis is to create a comprehensive model of the device that predicts both static and dynamic responses of the magnetization to applied stress. The model will be used to interface the device with CMOS controllers and switches in large systems. Next, in an attempt to speed up the simulation of such devices in multi-megabyte memory systems, a liberal model has been developed by analytically approximating a solution to the magnetization dynamics, which should be numerically solved otherwise. The liberal model demonstrates more than two orders of magnitude speed improvement compared to the conventional numerical models. Highlighting the applications of the straintronics devices by combining such devices with peripheral CMOS circuitry is another goal of the research. Design of a proof-of-concept 2 kilo-bit nonvolatile straintronics-based memory was introduced in our recent work. To highlight the potential applications of the straintronics device, beyond data storage, the use of the principle in ultra-fast yet low power true random number generation and neuron/synapse design for artificial neural networks have been investigated. Lastly, in an attempt to investigate the practicality of the straintronics principle, the effect of process variations and interface imperfections on the switching behavior of the magnetization is investigated. The results reveal the destructive aftermath of fabrication imperfections on the switching pattern of the device, leaving careful pulse-shaping, alternative topologies, or combination with STT as the last resorts for successful strain-based magnetization switching.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137010/1/barangi_1.pd

Developing Organic Electrochemical Electronics from Fundamentals to Integrated Circuit Components

Heutzutage werden riesige Datenmengen zwischen Endgeräten und Cloud-Servern verschoben. Cloud-Computing war nach Bloomberg bereits für 1% des weltweiten Stromverbrauchs im Jahr 2021 verantwortlich. Darüber hinaus kann die monopolartige Speicherung personenbezogener Daten schwerwiegende Auswirkungen auf die Gesellschaften unserer Welt haben. Um persönlichen Datenschutz und einen nachhaltigen Energieverbrauch zu gewährleisten, bedarf es einer Datenverarbeitung direkt am Endgerät; bezeichnet als Edge Computing. In diesem Zuge wird die Nachfrage nach individuell gestalteten Edge-Geräten rapide ansteigen. Der neu entstehende Markt bietet der organischen elektrochemischen Elektronik eine große Chance, vor allem für bioelektronische Anwendungen; allerdings muss die Chipintegration verbessert werden. In dieser Arbeit habe ich elektrochemische organische Elektronik für die Integration in Computersysteme untersucht. Insbesondere habe ich einen festen, photostrukturierbaren Elektrolyten entwickelt, der die Integration von OECTs ohne Kreuzkommunikation zwischen Bauteilen ermöglicht. Die OECTs arbeiten bei Spannungen unter 1V und schalten mit einem großen An/Aus-Verhältnis von 5 Größenordnungen und einer Unterschwellenschwingung nahe des thermodynamischen Minimums von 60mV/Dekade. Darüber hinaus wurden bei der Untersuchung der Hysterese des Bauelements drei verschiedene Hystereseregime identifiziert. Anschließend untersuchte ich die Schaltdynamik des OECTs und demonstrierte ein Top-Gate-OECT mit einer maximalen Betriebsfrequenz von 1 kHz. Beim Versuch, die komplexe Wechselwirkung zwischen Ionen und Elektronen in integrierten OECTs zu verstehen, habe ich einen grundlegenden elektrochemischen Mechanismus identifiziert. Die Abhängigkeit dieses Mechanismus’ von der Gate-Größe und der Drain-Überlapplänge wurde aufgezeigt und dieses Wissen zur Optimierung elektrochemischer Inverter genutzt. Zur Darstellung von OECT-basierten Schaltungskomponenten habe ich verschiedene Halbleiter verwendet und entsprechende Inverter hergestellt. Schließlich wurde die Hysterese eines einzigen ambipolaren Inverters zur Demonstration eines dynamischen Klinkenschalters genutzt. Im Rahmen dieser Arbeit habe ich die OECT-Technologie von den Anfängen bis hin zu integrierten Schaltkreiskomponenten entwickelt. Ich glaube, dass diese Arbeit ein Startschuss für Wissenschaftler und Ingenieure sein wird, um die OECT-Technologie in der realen Welt des Edge Computing einzusetzen.Nowadays, vast amounts of data are shuttled between end-user devices and cloud servers. This cloud computing paradigm was, according to Bloomberg, already responsible for 1% of the world’s electricity usage in 2021. Moreover, the monopoly-like storage of personal data can have a severe impact on the world’s societies. To guarantee data privacy and sustainable energy consumption in future, data computation directly at the end-user site is mandatory. This computing paradigm is called edge computing. Owing to the vast amount of end-user-specific applications, the demand for individually designed edge devices will rapidly increase. In this newly approaching market, organic electrochemical electronics offer a great opportunity, especially for bioelectronic applications; however, the integration into low-power-consuming systems has to be improved. In this work, I investigated electrochemical organic electronics for their integration into computational systems. In particular, I developed a solid photopatternable electrolyte that allows integrating organic electrochemical transistors (OECTs) without cross-talk between adjacent devices. The OECTs operate at voltages below 1 V, and exhibit a large on/off ratio of 5 orders of magnitude and a subthreshold-swing close to the thermodynamic minimum of 60mV/dec. Moreover, investigating the device’s hysteresis, three distinct hysteresis regimes were identified; the RC-time-dominated regime I, the retention time governed regime II, and the time-independent stable regime III. I then examined the OECT’s switching dynamics and, subsequently, demonstrated a top-gate device with a maximum operating frequency of 1 kHz. Trying to understand the complex interaction between ions and electrons in integrated OECTs, I disclosed a fundamental electrochemical mechanism and named it the electrochemical electrode coupling (EEC). The EEC’s dependence on gate size and drain overlap length was rigorously shown, and this knowledge was used to optimize electrochemical inverters. Yet, to exemplify OECT-based circuit components, I employed various semiconductors and fabricated five inverters, each with its unique advantage. Finally, the ambipolar inverter’s hysteresis was used to demonstrate a single-device dynamic latch, a basic in-memory computational element. In this thesis, I developed the OECT technology from an infancy stage to integrated circuit components. I believe that this work will be a starting signal for scientists and engineers to bring the OECT technology into real-world edge computing

Circuit Design

Circuit Design = Science + Art! Designers need a skilled "gut feeling" about circuits and related analytical techniques, plus creativity, to solve all problems and to adhere to the specifications, the written and the unwritten ones. You must anticipate a large number of influences, like temperature effects, supply voltages changes, offset voltages, layout parasitics, and numerous kinds of technology variations to end up with a circuit that works. This is challenging for analog, custom-digital, mixed-signal or RF circuits, and often researching new design methods in relevant journals, conference proceedings and design tools unfortunately gives the impression that just a "wild bunch" of "advanced techniques" exist. On the other hand, state-of-the-art tools nowadays indeed offer a good cockpit to steer the design flow, which include clever statistical methods and optimization techniques.Actually, this almost presents a second breakthrough, like the introduction of circuit simulators 40 years ago! Users can now conveniently analyse all the problems (discover, quantify, verify), and even exploit them, for example for optimization purposes. Most designers are caught up on everyday problems, so we fit that "wild bunch" into a systematic approach for variation-aware design, a designer's field guide and more. That is where this book can help! Circuit Design: Anticipate, Analyze, Exploit Variations starts with best-practise manual methods and links them tightly to up-to-date automation algorithms. We provide many tractable examples and explain key techniques you have to know. We then enable you to select and setup suitable methods for each design task - knowing their prerequisites, advantages and, as too often overlooked, their limitations as well. The good thing with computers is that you yourself can often verify amazing things with little effort, and you can use software not only to your direct advantage in solving a specific problem, but also for becoming a better skilled, more experienced engineer. Unfortunately, EDA design environments are not good at all to learn about advanced numerics. So with this book we also provide two apps for learning about statistic and optimization directly with circuit-related examples, and in real-time so without the long simulation times. This helps to develop a healthy statistical gut feeling for circuit design. The book is written for engineers, students in engineering and CAD / methodology experts. Readers should have some background in standard design techniques like entering a design in a schematic capture and simulating it, and also know about major technology aspects