A fine-grain time-sharing Time Warp system

Although Parallel Discrete Event Simulation (PDES) platforms relying on the Time Warp (optimistic) synchronization protocol already allow for exploiting parallelism, several techniques have been proposed to further favor performance. Among them we can mention optimized approaches for state restore, as well as techniques for load balancing or (dynamically) controlling the speculation degree, the latter being specifically targeted at reducing the incidence of causality errors leading to waste of computation. However, in state of the art Time Warp systems, events’ processing is not preemptable, which may prevent the possibility to promptly react to the injection of higher priority (say lower timestamp) events. Delaying the processing of these events may, in turn, give rise to higher incidence of incorrect speculation. In this article we present the design and realization of a fine-grain time-sharing Time Warp system, to be run on multi-core Linux machines, which makes systematic use of event preemption in order to dynamically reassign the CPU to higher priority events/tasks. Our proposal is based on a truly dual mode execution, application vs platform, which includes a timer-interrupt based support for bringing control back to platform mode for possible CPU reassignment according to very fine grain periods. The latter facility is offered by an ad-hoc timer-interrupt management module for Linux, which we release, together with the overall time-sharing support, within the open source ROOT-Sim platform. An experimental assessment based on the classical PHOLD benchmark and two real world models is presented, which shows how our proposal effectively leads to the reduction of the incidence of causality errors, as compared to traditional Time Warp, especially when running with higher degrees of parallelism

A case study for NoC based homogeneous MPSoC architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo

On The Modeling of OpenFlow-based SDNs: The Single Node Case

OpenFlow is one of the most commonly used protocols for communication between the controller and the forwarding element in a software defined network (SDN). A model based on M/M/1 queues is proposed in [1] to capture the communication between the forwarding element and the controller. Albeit the model provides useful insight, it is accurate only for the case when the probability of expecting a new flow is small. Secondly, it is not straight forward to extend the model in [1] to more than one forwarding element in the data plane. In this work we propose a model which addresses both these challenges. The model is based on Jackson assumption but with corrections tailored to the OpenFlow based SDN network. Performance analysis using the proposed model indicates that the model is accurate even for the case when the probability of new flow is quite large. Further we show by a toy example that the model can be extended to more than one node in the data plane.Comment: Published in Proceedings of CS & IT for NeCOM 201

Modeling and simulation of data communication networks using SARA

The selection of an appropriate simulation language can have a profound impact on the success of a simulation study. The available options range from domain-specific simulation languages to general-purpose programming languages. These languages are often supported by a collection of tools which form a simulation system. This paper examines UCLA's SARA (Systems ARchitects' Apprentice) system and explores its' usefulness in modeling and simulating a data communications network. Based on experimental use of SARA's tools, the system is evaluated with respect to required expertise, modeling power, as well as measurement and reporting capability

pandapower - an Open Source Python Tool for Convenient Modeling, Analysis and Optimization of Electric Power Systems

pandapower is a Python based, BSD-licensed power system analysis tool aimed at automation of static and quasi-static analysis and optimization of balanced power systems. It provides power flow, optimal power flow, state estimation, topological graph searches and short circuit calculations according to IEC 60909. pandapower includes a Newton-Raphson power flow solver formerly based on PYPOWER, which has been accelerated with just-in-time compilation. Additional enhancements to the solver include the capability to model constant current loads, grids with multiple reference nodes and a connectivity check. The pandapower network model is based on electric elements, such as lines, two and three-winding transformers or ideal switches. All elements can be defined with nameplate parameters and are internally processed with equivalent circuit models, which have been validated against industry standard software tools. The tabular data structure used to define networks is based on the Python library pandas, which allows comfortable handling of input and output parameters. The implementation in Python makes pandapower easy to use and allows comfortable extension with third-party libraries. pandapower has been successfully applied in several grid studies as well as for educational purposes. A comprehensive, publicly available case-study demonstrates a possible application of pandapower in an automated time series calculation

Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281