Dual material gate field effect transistor (DMG-FET)

Improving performance and suppressing short channel effects are two of the most important issues in present field effect transistors development. Hence, high performance and long channel like behaviors are essential requirements for short channel FETs. This dissertation focuses on new ways to achieve these significant goals. A new field effect transistor - dual material gate FET (DMG-FET) - is presented for the first time. The unique feature of the DMG-FET is its gate which consists of two laterally contacting gate materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that charge carriers are accelerated more rapidly in the channel and the channel potential near the source is screened from the drain bias after saturation. Using HFET as a vehicle, it is shown that the drive current and transconductance in DMG-FET are therefore substantially enhanced as compared to conventional FET. Moreover, it is observed that the short channel effects such as channel length modulation, DIBL and hot-carrier effect are significantly suppressed. Numerical simulations are employed to investigate the new device structure and related phenomenon. A simple and practical DMG-HFET fabrication process has been developed. The proposed DMG-HFET is thus realized for the first time. Experimental results exhibit improved characteristics as the simulation results predicted

Computer Simulation and Device Physics of SiGe Heterojunction Bipolar Transistors

Recent advances in semiconductor growth technology have enabled the growth of SiGe strained layers on silicon substrates. Si/SiGe technology has a promising future, especially in microwave HBT applications. This work describes the development of an existing two-dimensional drift-diffusion device simulation program for accurate modelling of SiGe heterojunction bipolar transistors (HBT\u27s). PUPHS2D (Purdue University Program for Heterostructure Simulation in Two Dimensions) was formulated by Paul Dodd [Dod89] as an AlGaAs/GaAs HBT simulation tool. This work describes the extension of this program to the silicon and Si 1|_xGex material systems. The computer model allows the user to explore internal device physics as well as terminal characteristics of a device. Field-dependent mobility has been added to the program in order to more accurately compute high-field transport phenomena. The simulation tool is used to study the performance of silicon bipolar transistors and Si/SiGe HBT\u27s, and these results are presented in chapter 4

Ensemble Monte Carlo Based Simulation Analysis of GaN HEMTs for High-Power Microwave Device Applications

The high electron mobility transistors (HEMTs) fabricated using wide-bandgap semiconductors show promise as high-gain, low-noise devices with superior frequency response. The structure and operation principle of HEMT are first briefly discussed. The distinguishing and unique properties of GaN are reviewed and compared with those of GaAs. Calculations of the electronic mobility and drift velocity have been carried out for bulk GaN based on a Monte Carlo approach, which serves as a validity check for the simulation model. By taking account of polarization effects, degeneracy and interface roughness scattering, important microwave performance measures such as the dynamic range, harmonic distortion and inter-modulation characteristics are fully studied. Monte Carlo based calculations of the large-signal nonlinear response characteristics of GaN-AlGaN HEMTs with particular emphasis on intermodulation distortion (IMD) have been performed. The nonlinear electrical transport is treated on first principles, including all scattering mechanisms. Both memory and distributed effects are built into the model. The results demonstrate an optimal operating point for low intermodulation distortion (IMD) at reasonably large output power due to the exist of a minima in the IMD curve. Dependence of the nonlinear characteristics on the barrier mole fraction “x” is also demonstrated and analyzed. High-temperature predictions of the IMD have also been made by carrying out the simulations at 600 K. Due to a relative suppression of interface roughness scattering, an increase in dynamic range with temperature is predicted. Finally, towards the end of the research, real-space transfer (RST) phenomena are included in the Monte Carlo simulator to accurately describe the electron transport behavior in HEMTs. The RST is shown to affect the velocity overshoot and inter-modulation distortion behavior and to lead to enhanced substrate leakage current as well as lowered overall performance speed. The potential for drain current compression has also been examined through simulations. Comparisons with and without RST have been performed based on Monte Carlo simulations. Results show that the velocity, IMD and dynamic range are all affected by the applied bias, temperature, internal electric field and gate length characteristics

Monte Carlo simulation of silicon-germanium transistors

Self-consistent Monte Carlo simulation studies of n-channel Si/SiGe modulation doped field effect transistors (MODFETs) and silicon-on-insulator lateral bipolar junction transistors (SOI- LBJTs) are reported in this thesis. As a preliminary to the device studies Monte Carlo simulations of electron transport in bulk Si strained as if grown on Si(_0.77)Ge(_0.23) and Si(_0.55)Ge(_0.45) substrates have been carried out at 300 K, for field strengths varied from 10(^4) to 2 x 10(^7) Vm(^-1). The calculations indicate an enhancement of the average electron drift velocity when Si is tensilely strained in the growth plane. The enhancement of electron velocity is more marked at low and intermediate electric fields, while at very high fields the velocity saturates at about the same value as unstrained Si. In addition the ensemble Monte Carlo method has been used to study the transient response to a stepped electric field of electrons in strained and unstrained Si. The calculations suggest that significant velocity overshoots occurs in strained material. Simulations of n-channel Si/Si(_1=z)Ge(_z) MODFETs with Ge fractions of 0.23, 0.25, and 0.45 have been performed. Five depletion mode devices with x = 0.23 and 0.25 were studied. The simulations provide information on the microscopic details of carrier behaviour, including carrier velocity, kinetic energy and carrier density, as a function of position in the device. Detailed time-dependent voltage signal analysis has been carried out to test device response and derive the frequency bandwidth. The simulations predict a current gain cut-off frequency of 60 ± 10 GHz for a device with a gate length of 0.07 /nm and a channel length of 0.25 um. Similar studies of depletion and enhancement mode n-channel Si/Sio.55Geo.45 MODFETs with a gate length of 0.18 /im have been carried out. Cut-off frequencies of 60 ±10 GHz and 90± 10 GHz are predicted for the depletion and enhancement mode devices respectively. A Monte Carlo model has also been devised and used to simulate steady state and transient electron and hole transport in SOI-LBJTs. Four devices have been studied and the effects of junction depth and silicon layer thickness have been investigated. The advantage of the silicon-on-insulator technology SOI device is apparent in terms of higher collector current, current gain, and cut-off frequency obtained in comparison with an all-silicon structure. The simulations suggest that the common-emitter current gain of the most promising SOI-LBJT structure considered could have a cut-off frequency approaching 35 ± 5 GHz

Microwave characterization of vertical cavity surface emitting diode laser and transistor laser

Semiconductor lasers are widely deployed in optical transceivers for optical fiber based short-reach (< 100m) data links. With increasingly growing data traffic worldwide in data centers, developments of faster optical transceivers, hence high-speed semiconductor lasers, are highly demanded. The vertical cavity surface-emitting laser (VCSEL) is the most commercially popular choice. With high reflectivity DBR mirrors and oxide-confinement for emission mode control and leakage current reduction, VCSELs are able to achieve a low laser threshold and high modulation bandwidth. Currently in published research results, the highest data transmission rate demonstrated for an 850 nm VCSEL is 57 Gb/s error-free at 25 °C and 50 Gb/s error-free at 85 °C. Nevertheless, the bandwidth and data transmission performance of diode lasers, such as VCSELs, are fundamentally limited by the slow spontaneous recombination lifetime. Therefore, a new kind of semiconductor laser, the transistor laser (TL), is proposed to break the bandwidth bottleneck as the dynamic carrier transport in the base of a TL drastically reduces the spontaneous recombination lifetime. Ultimately to reach low threshold and high energy per bit efficiency, the first oxide-confined vertical cavity transistor laser (VCTL) is realized with a trench oxidation process and a lateral-feeding base metal design. To further reduce the excessive emitter series resistance, a VCTL with partially etched mesa is developed and fabricated. The tunneling modulation aspect and possible application of the TL is also explored in this dissertation

Modeling Of Two Dimensional Graphene And Non-graphene Material Based Tunnel Field Effect Transistors For Integrated Circuit Design

The Moore’s law of scaling of metal oxide semiconductor field effect transistor (MOSFET) had been a driving force toward the unprecedented advancement in development of integrated circuit over the last five decades. As the technology scales down to 7 nm node and below following the Moore’s law, conventional MOSFETs are becoming more vulnerable to extremely high off-state leakage current exhibiting a tremendous amount of standby power dissipation. Moreover, the fundamental physical limit of MOSFET of 60 mV/decade subthreshold slope exacerbates the situation further requiring current transport mechanism other than drift and diffusion for the operation of transistors. One way to limit such unrestrained amount of power dissipation is to explore novel materials with superior thermal and electrical properties compared to traditional bulk materials. On the other hand, energy efficient steep subthreshold slope devices are the other possible alternatives to conventional MOSFET based on emerging novel materials. This dissertation addresses the potential of both advanced materials and devices for development of next generation energy efficient integrated circuits. Among the different steep subthreshold slope devices, tunnel field effect transistor (TFET) has been considered as a promising candidate after MOSFET. A superior gate control on source-channel band-to-band tunneling providing subthreshold slopes well below than 60 mV/decade. With the emergence of atomically thin two-dimensional (2D) materials, interest in the design of TFET based on such novel 2D materials has also grown significantly. Graphene being the first and the most studied among 2D materials with exotic electronic and thermal properties. This dissertation primarily considers current transport modeling of graphene based tunnel devices from transport phenomena to energy efficient integrated circuit design. Three current transport models: semi-classical, semi-quantum and numerical simulations are described for the modeling of graphene nanoribbon tunnel field effect transistor (GNR TFET) where the semi-classical model is in close agreement with the quantum transport simulation. Moreover, the models produced are also extended for integrated circuit design using Verilog-A hardware description language for logic design. In order to overcome the challenges associated with the band gap engineering for making graphene transistor for logic operation, the promise of graphene based interlayer tunneling transistors are discussed along with their existing fundamental physical limitation of subthreshold slope. It has been found that such interlayer tunnel transistor has very poor electrostatic gate control on drain current. It gives subthreshold slope greater than the thermionic limit of 60 mV/decade at room temperature. In order to resolve such limitation of interlayer tunneling transistors, a new type of transistor named “junctionless tunnel effect transistor (JTET)” has been invented and modeled for the first time considering graphene-boron nitride (BN)-graphene and molybdenum disulfide (MoS2)-boron nitride (BN) heterostructures, where the interlayer tunneling mechanism controls the source-drain ballistic transport instead of depleting carriers in the channel. Steep subthreshold slope, low power and high frequency THz operation are few of the promising features studied for such graphene and MoS2 JTETs. From current transport modeling to energy efficient integrated circuit design using Verilog-A has been carried out for these new devices as well. Thus, findings in this dissertation would suggest the exciting opportunity of a new class of next generation energy efficient material based transistors as switches

Journal of Telecommunications and Information Technology, 2004, nr 1

kwartalni

Simulation and Optimisation of SiGe MOSFETs

This research project is concerned with the development of methodology for simulating advanced SiGe MOSFETs using commercial simulators, the calibration of simulators against higher level Monte Carlo simulation results and real device measurements, and the application of simulation tools in the design of next generation p- channel devices. The methodology for the modelling and simulation of SiGe MOSFET devices is outlined. There are many simulation approaches widely used to simulate SiGe devices, such as Monte Carlo, hydrodynamic, energy transport, and drift diffusion. Different numerical techniques including finite difference, finite box and finite element methods, may be used in the simulators. The Si0.8Ge0.2 p-MOSFETs fabricated especially for high-field transport studies and the Si0.64Ge0.36 p-channel MOSFETs fabricated at Warwick and Southampton Universities with a CMOS compatible process in varying gate lengths were calibrated and investigated. Enhanced low field mobility in SiGe layers compared to Si control devices was observed. The results indicated that the potential of velocity overshoot effects for SiGe p-MOSFETs was considerably higher than Si counterparts, promising higher performance in the former at equal gate lengths at ultra-small devices. The effects of punchthrough stopper, undoped buffers and delta doping for SiGe p-MOSFETs were analysed systematically. It was found that the threshold voltage roll off might be reduced considerably by using an appropriate punchthrough stopper. In order to adjust the threshold voltage for digital CMOS applications, p-type delta doping was required for n+-polysilicon gate p-MOSFET. The use of delta doping made the threshold voltage roll off a more serious issue, therefore delta doping should be used with caution. The two-dimensional process simulator TSUPREM-4 and the two-dimensional device simulator MEDICI were employed to optimise and design Si/SiGe hybrid CMOS. The output of TSUPREM-4 was transferred automatically to the MEDICI device simulator. This made the simulation results more realistic. For devices at small gate length, lightly doped drain (LDD) structures were required. They would decrease the lateral subdiffusion and allow threshold voltage roll off to be minimised. These structures, however, would generally reduce drain current due to an increase in the series resistance of the drain region. Further consideration must be made of these trade-offs. Comparison between drift diffusion and hydrodynamic simulation results for SiGe p-MOSFETs were presented for the first time, with transport parameters extracted from our in-house full-band hole Monte Carlo transport simulator. It was shown that while drift diffusion and hydrodynamic simulations provided a reasonable estimation of the I-V characteristics for Si devices, the same could not be said for aggressively scaled SiGe devices. The resulting high fields at the source end of the devices meant that nonequilibrium transport effects were significant. Therefore for holes, models based on an isotropic carrier temperature were no longer appropriate, as it was shown by analysing the tensor components of the carrier temperature obtained from Monte Carlo simulation. Two-dimensional drift diffusion and Monte Carlo simulations of well-tempered Si p-MOSFETs with gate lengths of 25 and 50 nm were performed. By comparing Monte Carlo simulations with carefully calibrated drift diffusion results, it was found that nonequilibrium transport was important for understanding the high current device characteristics in sub 0.1 mum p-MOSFETs. The well-tempered devices showed better characteristics than the conventional SiGe devices. Both threshold voltage roll off and the subthreshold slope were acceptable although the effective channel length of this device was reduced from 50 nm to 25 nm. In order to adjust the threshold voltage for the digital CMOS applications, p-type delta doping was used for 50 nm well-tempered SiGe p- MOSFETs. As the delta doping made the threshold voltage roll off too serious, it was not suitable for 25 nm well-tempered SiGe p-MOSFETs

A heterojunction bipolar transistor with stepwise allog-graded base : analysis, design, fabrication, and characterization

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 117-126).(cont.) features but the device self-heating turned out to be crucial for the longevity of the base micro-airbridges. The short lifetime of the base micro-airbridges was prohibitive for the realization of high frequency measurements. This work serves as the foundation for the implementation of robust HBT transit-time oscillators with the incorporation of slight modifications in the fabrication process.This thesis explores the potential benefits of a GaAs-based heterojunction bipolar transistor (HBT) with stepwise alloy-graded base. The step height is slightly greater than the longitidinal optical (LO) phonon energy h[omega]LO in order to facilitate LO-phonon-enhanced forward diffusion of minority carriers in the base. The intuitive theoretical approach of carrier transport in the base, as proposed by other workers for this type of alloy-grading, did not incorporate in detail the various mechanisms of transport. In this work, we solved the Botzmann transport equation (BTE) in one dimension across the base for arbritrary frequencies. Impurity and LO phonon scattering were considered as the dominant scattering mechanisms. The intrinsic and extrinsic elements were combined and a small-signal equivalent circuit was proposed for the evaluation of the high-frequency performance of the device. The unique feature of this HBT is that the base transport factor undergoes a moderate magnitude attenuation and phase delay. By choosing a suitable collector delay, a band-limited negative output resistance can emerge in the microwave/millimeter-wave regime. The main benefit of the device is its inherent property as a transit-time high-frequency oscillator. Using our device simulator, we selected the material parameters for epitaxial growth (MBE) of the device wafer and we investigated various device layouts. We implemented the complete microfabrication of 2 [micro]m x 15 [micro]m, self-aligned, emitter-up HBTs with micro-airbridges for device isolation purposes. We performed DC measurements of various devices and they provided us with feedback for modifications in the MBE design and growth conditions of the device wafer. We finally fabricated HBTs with favorable DCby Konstantinos Konistis.Ph.D