Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area

Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability

Despite power boundaries, Moore's law is still present via scaling the number of cores, which keeps adding demands for more memory bandwidth (MBW) requested by these cores. To obtain higher MBW levels, it is fundamental to address memory controller (MC) scalability. However, MC scalability growth is limited by I/O pin counts scaling. To underline MC and pin scaling, a radio frequency(RF) I/O pad-scalable package-based (RFiop) memory organization is further investigated. In RFiop, a RF pad (RFpad) is defined as a quilt-packaging (QP) coplanar waveguide employed at RF ranges. An RFpad connects a rank to an RFMC which is formed by coupling MCs to RF transmitter/receivers. By using QP package to explore the architectural benefits of laying out ranks, RFiop replaces the traditional memory path with an RF-based one, while exploring the scalability of RFpads/RFMCs via RF signaling. When evaluating RFiop, our findings show that MBW/performance are enhanced by around 4.3x which can be viewed as a diminution in transaction queue occupancy/latency as well as using a reduced and scalable 4-8 RFpads per RFMC. RFiop architectural area benefits allow MBW/performance improvements of around 3.2x, while reducing interconnection energy up to 78%

Interconnects architectures for many-core era using surface-wave communication

PhD ThesisNetworks-on-chip (NoCs) is a communication paradigm that has emerged aiming to address on-chip communication challenges and to satisfy interconnection demands for chip-multiprocessors (CMPs). Nonetheless, there is continuous demand for even higher computational power, which is leading to a relentless downscaling of CMOS technology to enable the integration of many-cores. However, technology downscaling is in favour of the gate nodes over wires in terms of latency and power consumption. Consequently, this has led to the era of many-core processors where power consumption and performance are governed by inter-core communications rather than core computation. Therefore, NoCs need to evolve from being merely metalbased implementations which threaten to be a performance and power bottleneck for many-core efficiency and scalability. To overcome such intensified inter-core communication challenges, this thesis proposes a novel interconnect technology: the surface-wave interconnect (SWI). This new RF-based on-chip interconnect has notable characteristics compared to cutting-edge on-chip interconnects in terms of CMOS compatibility, high speed signal propagation, low power dissipation, and massive signal fan-out. Nonetheless, the realization of the SWI requires investigations at different levels of abstraction, such as the device integration and RF engineering levels. The aim of this thesis is to address the networking and system level challenges and highlight the potential of this interconnect. This should encourage further research at other levels of abstraction. Two specific system-level challenges crucial in future many-core systems are tackled in this study, which are cross-the-chip global communication and one-to-many communication. This thesis makes four major contributions towards this aim. The first is reducing the NoC average-hop count, which would otherwise increase packet-latency exponentially, by proposing a novel hybrid interconnect architecture. This hybrid architecture can not only utilize both regular metal-wire and SWI, but also exploits merits of both bus and NoC architectures in terms of connectivity compared to other general-purpose on-chip interconnect architectures. The second contribution addresses global communication issues by developing a distance-based weighted-round-robin arbitration (DWA) algorithm. This technique prioritizes global communication to be send via SWI short-cuts, which offer more efficient power dissipation and faster across-the-chip signal propagation. Results obtained using a cycleaccurate simulator demonstrate the effectiveness of the proposed system architecture in terms of significant power reduction, considervii able average delay reduction and higher throughput compared to a regular NoC. The third contribution is in handling multicast communications, which are normally associated with traffic overload, hotspots and deadlocks and therefore increase, by an order of magnitude the power consumption and latency. This has been achieved by proposing a novel routing and centralized arbitration schemes that exploits the SWI0s remarkable fan-out features. The evaluation demonstrates drastic improvements in the effectiveness of the proposed architecture in terms of power consumption ( 2-10x) and performance ( 22x) but with negligible hardware overheads ( 2%). The fourth contribution is to further explore multicast contention handling in a flexible decentralized manner, where original techniques such as stretch-multicast and ID-tagging flow control have been developed. A comparison of these techniques shows that the decentralized approach is superior to the centralized approach with low traffic loads, while the latter outperforms the former near and after NoC saturation

Silicon Modulators, Switches and Sub-systems for Optical Interconnect

Silicon photonics is emerging as a promising platform for manufacturing and integrating photonic devices for light generation, modulation, switching and detection. The compatibility with existing CMOS microelectronic foundries and high index contrast in silicon could enable low cost and high performance photonic systems, which find many applications in optical communication, data center networking and photonic network-on-chip. This thesis first develops and demonstrates several experimental work on high speed silicon modulators and switches with record performance and novel functionality. A 8x40 Gb/s transmitter based on silicon microrings is first presented. Then an end-to-end link using microrings for Binary Phase Shift Keying (BPSK) modulation and demodulation is shown, and its performance with conventional BPSK modulation/ demodulation techniques is compared. Next, a silicon traveling-wave Mach- Zehnder modulator is demonstrated at data rate up to 56 Gb/s for OOK modulation and 48 Gb/s for BPSK modulation, showing its capability at high speed communication systems. Then a single silicon microring is shown with 2x2 full crossbar switching functionality, enabling optical interconnects with ultra small footprint. Then several other experiments in the silicon platform are presented, including a fully integrated in-band Optical Signal to Noise Ratio (OSNR) monitor, characterization of optical power upper bound in a silicon microring modulator, and wavelength conversion in a dispersion-engineered waveguide. The last part of this thesis is on network-level application of photonics, specically a broadcast-and-select network based on star coupler is introduced, and its scalability performance is studied. Finally a novel switch architecture for data center networks is discussed, and its benefits as a disaggregated network are presented

Millimeter-wave interconnects for intra- and inter-chip transmission and beam steering in NoC-based multi-chip systems

The primary objective of this work is to investigate the communication capabilities of short-range millimeter-wave (mm-wave) communication among Network-on-Chip (NoC) based multi-core processors integrated on a substrate board. To address the demand for high-performance multi-chip computing systems, the present work studies the transmission coefficients between the on-chip antennas system for both intra- and inter-chip communication. It addresses techniques for enhancing transmission by using antenna arrays for beamforming. It also explores new and creative solutions to minimize the adverse effects of silicon on electromagnetic wave propagation using artificial magnetic conductors (AMC). The following summarizes the work performed and future work. Intra- and inter-chip transmission between wireless interconnects implemented as antennas on-chip (AoC), in a wire-bonded chip package are studied 30GHz and 60 GHz. The simulations are performed in ANSYS HFSS, which is based on the finite element method (FEM), to study the transmission and to analyze the electric field distribution. Simulation results have been validated with fabricated antennas at 30 GHz arranged in different orientations on silicon dies that can communicate with inter-chip transmission coefficients ranging from -45dB to -60dB while sustaining bandwidths up to 7GHz. The fabricated antennas show a shift in the resonant frequency to 25GHz. This shift is attributed to the Ground-Signal-Ground (GSG) probes used for measurement and to the Short-Open-Load (SOLT) calibration which has anomalies at millimeter-wave frequencies. Using measurements, a large-scale log-normal channel model is derived which can be used for system-level architecture design. Further, at 60 GHz densely packed multilayer copper wires in NoCs have been modeled to study their impact on the wireless transmission between antennas for both intra- and inter-chip links and are shown to be equivalent to copper sheets. It is seen that the antenna radiation efficiency reduces in the presence of these densely packed wires placed close to the antenna elements. Using this model, the reduction of inter-chip transmission is seen to be about 20dB as compared to a system with no wires. Lastly, the transmission characteristics of the antennas resonating at 60GHz in a flip-chip packaging environment are also presented

Development of the recess mounting with monolithic metallization optoelectronic integrated circuit technology for optical clock distribution applications

Thesis (Elec. E.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 123-128).Recess mounting with monolithic metallization, or RM3 integration, is used to integrate Ino.47Ga0.53As/InP based lattice-matched high quantum efficiency p-i-n photodetectors on silicon chips to build high performance optoelectronic integrated circuits [1]. In RM3 integration, partially processed heterostructure devices are placed in recesses formed in the dielectric layers covering the surface of an integrated circuit chip, the surface is planarized, and monolithic processing is continued to transform the heterostructures into optoelectronic devices monolithically integrated with the underlying electronic circuitry. Two different RM3 techniques have been investigated, Aligned Pillar Bonding (APB) and OptoPill Assembly (OPA). APB integrates lattice mismatched materials using aligned, selective area wafer bonding at reduced temperature (under 3500C), which protects the electronic chips from the adverse effects of high temperatures, and reduces the thermal expansion mismatch concerns. In the OPA technique, optoelectronic heterostructures are processed into circular pills of 8 gm height and 45 gm diameter, the pills are released from the substrate, and collected through a process that involves decanting.(cont.) The pills are then assembled into recesses on silicon chips using manual pick & place techniques, and they are bonded to the metal pads on the bottom surface of the recesses using a Cu-AuSn solder bond. A new magnet assisted bonding technique is utilized to obtain clamping pressure to form the solder bond. The gap between the pill and the surrounding recess is filled using BCB, which also provides good surface planarization.by Eralp Atmaca.Elec.E