408 research outputs found

    DESIGN, MODELING, OPTIMIZATION, AND BENCHMARKING OF INTERCONNECTS AND SCALING TECHNOLOGIES AND THEIR CIRCUIT AND SYSTEM LEVEL IMPACT

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    This research focuses on the future of integrated circuit (IC) scaling technologies at the device and back end of line (BEOL) level. This work includes high level modeling of different technologies and quantifying potential performance gains on a circuit and system level. From the device side, this research looks at the scaling challenges and the future scaling drivers for conventional charge-based devices implemented at the 7nm technology node and beyond. It examines the system-level performance of stacking device logic in addition to tunneling field effect transistors (TFET) and their potential as beyond-CMOS devices. Finally, this research models and benchmarks BEOL scaling challenges and evaluates proposed technological advancements such as metal barrier scaling for copper interconnects and replacing local interconnects with ruthenium. Potential impact on performance, power, and area of these interconnect technologies is quantified for fully placed and routed circuits.Ph.D

    Impact of self-heating on the statistical variability in bulk and SOI FinFETs

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    In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS โ€˜atomisticโ€™ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

    5nm ์ดํ•˜ 3D Transistors์˜ Self-Heating ๋ฐ ์ „์—ดํŠน์„ฑ๋ถ„์„ ์—ฐ๊ตฌ

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ปดํ“จํ„ฐ๊ณตํ•™๋ถ€, 2021.8. ์‹ ํ˜•์ฒ .In this thesis, Self-Heating Effect (SHE) is investigated using TCAD simulations in various Sub-10-nm node Field Effect Transistor (FET). As the node decreases, logic devices have evolved into 3D MOSFET structures from Fin-FET to Nanosheet-FET. In the case of 3D MOSFET, there are thermal reliability issues due to the following reasons: โ…ฐ) The power density of the channel is high, โ…ฑ) The channel structure surrounded by SiO2, โ…ฒ) The overall low thermal conductivity characteristics due to scaling down. Many papers introduce the analysis and prediction of temperature rise by SHE in the device, but there are no papers presenting the content of mitigation of temperature rise. Therefore, we have studied the methods of decreasing the maximum lattice temperature (TL,max) such as shallow trench isolation (STI) composition engineering in Fin-FET, thermal analysis according to DC/AC/duty cycle in nanowire-FET, and active region ( e.g., gate metal thickness, channel width, channel number etc..) optimization in nanosheet-FET. In addition, lifetime affected by hot carrier injection (HCI) / bias-temperature instability (BTI) is also analyzed according to various thermal relaxation methods presented.์ด ๋…ผ๋ฌธ์—์„œ๋Š” ๋‹ค์–‘ํ•œ Sub-10nm ๋…ธ๋“œ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ (FET)์—์„œ TCAD ์‹œ๋ฎฌ๋ ˆ์ด์…˜์„ ์‚ฌ์šฉํ•˜์—ฌ ์ž์ฒด ๋ฐœ์—ด ํšจ๊ณผ (SHE)๋ฅผ ์กฐ์‚ฌํ•ฉ๋‹ˆ๋‹ค. ๋…ธ๋“œ๊ฐ€ ๊ฐ์†Œํ•จ์— ๋”ฐ๋ผ ๋…ผ๋ฆฌ ์žฅ์น˜๋Š” Fin-FET์—์„œ Nanosheet-FET๋กœ 3D MOSFET ๊ตฌ์กฐ๋กœ ์ง„ํ™”ํ–ˆ์Šต๋‹ˆ๋‹ค. 3D MOSFET์˜ ๊ฒฝ์šฐ โ…ฐ) ์ฑ„๋„์˜ ์ „๋ ฅ ๋ฐ€๋„๊ฐ€ ๋†’์Œ, โ…ฑ) SiO2๋กœ ๋‘˜๋Ÿฌ์‹ธ์ธ ์ฑ„๋„ ๊ตฌ์กฐ, โ…ฒ) ์ถ•์†Œ๋กœ ์ธํ•ด ์ „์ฒด์ ์œผ๋กœ ๋‚ฎ์€ ์—ด์ „๋„ ํŠน์„ฑ ๋“ฑ ๋‹ค์Œ๊ณผ ๊ฐ™์€ ์ด์œ ๋กœ ์—ด ์‹ ๋ขฐ์„ฑ ๋ฌธ์ œ๊ฐ€ ์žˆ์Šต๋‹ˆ๋‹ค. ํ•œํŽธ, ๋งŽ์€ ๋…ผ๋ฌธ์ด device์—์„œ SHE์— ์˜ํ•œ ์˜จ๋„ ์ƒ์Šน์˜ ๋ถ„์„ ๋ฐ ์˜ˆ์ธก์„ ์†Œ๊ฐœํ•˜์ง€๋งŒ ์˜จ๋„ ์ƒ์Šน ์™„ํ™”์˜ ๋‚ด์šฉ์„ ์ œ์‹œํ•˜๋Š” ๋…ผ๋ฌธ์€ ๊ฑฐ์˜ ์—†์Šต๋‹ˆ๋‹ค. ๋”ฐ๋ผ์„œ Fin-FET์˜ STI (Shallow Trench Isolation) ๊ตฌ์„ฑ ๊ณตํ•™, nanowire-FET์˜ DC / AC / ๋“€ํ‹ฐ ์‚ฌ์ดํด์— ๋”ฐ๋ฅธ ์—ด ๋ถ„์„, nanosheet-FET์—์„œ ์†Œ์ž์˜ ์ค‘์š”์˜์—ญ(์˜ˆ: ๊ฒŒ์ดํŠธ ๊ธˆ์† ๋‘๊ป˜, ์ฑ„๋„ ํญ, ์ฑ„๋„ ๋ฒˆํ˜ธ ๋“ฑ)์˜ ์ตœ์ ํ™”๋ฅผ ํ†ตํ•ด์„œ ์ตœ๋Œ€ ๊ฒฉ์ž ์˜จ๋„ (TL,max)๋ฅผ ๋‚ฎ์ถ”๋Š” ๋ฐฉ๋ฒ•๋“ฑ์„ ์—ฐ๊ตฌํ–ˆ์Šต๋‹ˆ๋‹ค. ๋˜ํ•œ ๋” ๋‚˜์•„๊ฐ€์„œ HCI (Hot Carrier Injection) / BTI (Bias-Temperature Instability)์˜ ์˜ํ–ฅ์„ ๋ฐ›๋Š” ์ˆ˜๋ช…๋„ ์ œ์‹œ๋œ ๋‹ค์–‘ํ•œ ์—ด ์™„ํ™” ๋ฐฉ๋ฒ•์— ๋”ฐ๋ผ ๋ถ„์„ํ•˜์—ฌ ์†Œ์ž์˜ ์ œ์ž‘์— ์žˆ์–ด ์—ด์  ํŠน์„ฑ๊ณผ ์ˆ˜๋ช…์„ ์ข‹๊ฒŒ ๋งŒ๋“œ๋Š” ์ง€ํ‘œ๋ฅผ ์ œ์‹œํ•ฉ๋‹ˆ๋‹ค .Chapter 1 Introduction 1 1.1. Development of Semconductor structure 1 1.2. Self-Heating Effect issues in semiconductor devices 3 Chapter 2 Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing Ioff in Various Sub-10-nm 3-D Transistor 7 2.1. Introduction 7 2.2. Device Structure and Simulation Condition 7 2.3. Results and Discussion 12 2.4. Summary 27 Chapter 3 Analysis of Self Heating Effect in DC/AC Mode in Multi-channel GAA-Field Effect Transistor 32 3.1. Introduction 32 3.2. Multi-Channel Nanowire FET and Back End Of Line 33 3.3. Work Flow and Calibration Process 35 3.4. More Detailed Thermal Simulation of Nanowire-FET 37 3.5. Performance Analysis by Number of Channels 38 3.6. DC Characteristic of SHE in Nanowire-FETs 40 3.7. AC Characteristics of SHE in Nanowire-FETs 43 3.8. Summary 51 Chapter 4 Self-Heating and Electrothermal Properties of Advanced Sub-5-nm node Nanoplate FET 56 4.1. Introduction 56 4.2. Device Structure and Simulation Condition 57 4.3. Thermal characteristics by channel number and width 62 4.4. Thermal characteristics by inter layer-metal thickness (TM) 64 4.5. Life Time Prediction 65 4.6. Summary 67 Chapter 5 Study on Self Heating Effect and life time in Vertical-channel Field Effect Transistor 72 5.1. Introduction 72 5.2. Device Structure and Simulation Condition 72 5.3. Temperature and RTH according to channel width(TW) 76 5.4. Thermal properties according to air spacers and air gap 77 5.5. Ion boosting according to Channel numbers 81 5.6. Temperature imbalance of multi-channel VFETs 82 5.7. Mitigation of the channel temperature imbalance 86 5.8. Life time depending on various analysis conditions 88 5.9. Summary 89 Chapter 6 Conclusions 93 Appendix A. A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models 95 A.1. Introduction 95 A.2. Overall Schematic of the RF MOSFET Model 97 A.3. Verification of the DC Characteristics of the RF MOSFET Model 98 A.4. Verification of the MOSFET Model with Measured Y-parameters 100 A.5. Verification of the MOSFET Model with Measured Noise Parameters 101 A.6. Thermal Noise Extraction and Modeling (TNOIMOD = 0) 103 A.7. Verification of the Enhanced Model with Noise Parameters 112 A.8. Holistic Model (TNOIMOD = 1) 114 A.9. Evaluation the validity of the model for drain bias 115 A.10. Conclusion 117 Abstract in Korean 122๋ฐ•

    Characterization of self-heating effects and assessment of its impact on reliability in finfet technology

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    The systematically growing power (heat) dissipation in CMOS transistors with each successive technology node is reaching levels which could impact its reliable operation. The emergence of technologies such as bulk/SOI FinFETs has dramatically confined the heat in the device channel due to its vertical geometry and it is expected to further exacerbate with gate-all-around transistors. This work studies heat generation in the channel of semiconductor devices and measures its dissipation by means of wafer level characterization and predictive thermal simulation. The experimental work is based on several existing device thermometry techniques to which additional layout improvements are made in state of the art bulk FinFET and SOI FinFET 14nm technology nodes. The sensors produce excellent matching results which are confirmed through TCAD thermal simulation, differences between sensor types are quantified and error bars on measurements are established. The lateral heat transport measurements determine that heat from the source is mostly dissipated at a distance of 1ยตm and 1.5ยตm in bulk FinFET and SOI FinFET, respectively. Heat additivity is successfully confirmed to prove and highlight the fact that the whole system needs to be considered when performing thermal analysis. Furthermore, an investigation is devoted to study self-heating with different layout densities by varying the number of fins and fingers per active region (RX). Fin thermal resistance is measured at different ambient temperatures to show its variation of up to 70% between -40ยฐC to 175ยฐC. Therefore, the Si fin has a more dominant effect in heat transport and its varying thermal conductivity should be taken into account. The effect of ambient temperature on self-heating measurement is confirmed by supplying heat through thermal chuck and adjacent heater devices themselves. Motivation for this work is the continuous evolution of the transistor geometry and use of exotic materials, which in the recent technology nodes made heat removal more challenging. This poses reliability and performance concerns. Therefore, this work studies the impact of self-heating on reliability testing at DC conditions as well as realistic CMOS logic operating (AC) conditions. Front-end-of-line (FEOL) reliability mechanisms, such as hot carrier injection (HCI) and non-uniform time dependent dielectric breakdown (TDDB), are studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. By performing an HCI stress at moderate bias conditions, this dissertation shows that the laborious techniques of heat subtraction are no longer necessary. Self-heating is also studied at more realistic device switching conditions by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions and degradation is not distinguishable

    Bottom oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node

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    Structural advancements of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) without punch-through-stopper (PTS) were introduced using fully calibrated TCAD for the first time. It is challenging to scale down conventional bulk FinFETs into 5-nm technology node due to the sub-fin leakage increase. Meanwhile, bottom oxide deposition after anisotropic etching for source/drain (S/D) epi formation prevents the sub-fin leakage effectively even without the PTS doping, thus achieving better gate-to-channel controllability. Bottom oxide FinFETs also have smaller gate capacitances than do conventional FinFETs because the parasitic capacitances decrease by smaller S/D epi separated from the bottom Si layer, which reduces junction and outer-fringing capacitances. But smaller S/D epi decreases the stresses along the channel direction, and the effective widths decrease by the bottom oxide layer blocking the current paths at the bottom side of fin channels. Furthermore, increase of the interconnect resistance and capacitance parasitics down to 5-nm node diminishes the improvements of total delays as the interconnect wire length increases greatly. In spite of these drawbacks, 5-nm node bottom oxide FinFETs achieve smaller total delays than do the 7-nm node conventional FinFETs, especially for low-power applications, thus promising for the scalability of bulk FinFETs along with simple and reliable process by avoiding PTS step.11Ysciescopu

    Proposed Thermal Circuit Model for the Cost Effective Design of Fin FET

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    The Complementary metal-oxide-semiconductor (CMOS) device has been rapidly evolving and its size has been drastically decreasing ever since it was first fabricated in 1960 [Us Patent 3,356,858: 1967]. The substantial reduction in the CMOS device size has led to short channel effects which have resulted in the introduction of Fin Field Effect Transistor (FinFET), a tri-gate transistor built on a silicon on insulator (SOI) substrate. Furthermore, due to the geometry of the FinFET the severity of the heating problem has dramatically increased. Self-heating in the 3-dimensional FinFET device enhances the temperature gradients and peak temperature, which decrease drive current, increase the interconnect delays and degrade the device and interconnect reliability. In this work we have proposed a methodology to develop an accurate thermal model for the FinFET through a rigorous physics-based mathematical approach. A thermal circuit for the FinFET will be derived from the model. This model will allow chip designers to predict interconnect temperature which will lead them to achieve cost-effective design for the FinFET-based semiconductor chips. Keywords: Bulk CMOS, SOI CMOS, FinFET, Thermal heating

    Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

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    One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

    A COMPARATIVE STUDY OF RELIABILITY FOR FINFET

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    The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integrated Circuit (IC) density and performance. The emergence of FinFET technology has brought with it the same reliability issues as standard CMOS with the addition of a new prominent degradation mechanism. The same mechanisms still exist as for previous CMOS devices, including Bias Temperature Instability (BTI), Hot Carrier Degradation (HCD), Electro-migration (EM), and Body Effects. A new and equally important reliability issue for FinFET is the Self -heating, which is a crucial complication since thermal time-constant is generally much longer than the transistor switching times. FinFET technology is the newest technological paradigm that has emerged in the past decade, as downscaling reached beyond 20 nm, which happens also to be the estimated mean free path of electrons at room temperature in silicon. As such, the reliability physics of FinFET was modified in order to fit the newly developed transistor technology. This paper highlights the roles and impacts of these various effects and aging mechanisms on FinFET transistors compared to planar transistors on the basic approach of the physics of failure mechanisms to fit to a comprehensive aging model

    Analysis of performance variation in 16nm FinFET FPGA devices

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