72 research outputs found

    Development of a Technique for Characterizing Bias Temperature Instability-Induced Device-to-Device Variation at SRAM-Relevant Conditions

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    SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-(I) -(V) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias

    Degradation Models and Optimizations for CMOS Circuits

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    Die Gewährleistung der Zuverlässigkeit von CMOS-Schaltungen ist derzeit eines der größten Herausforderungen beim Chip- und Schaltungsentwurf. Mit dem Ende der Dennard-Skalierung erhöht jede neue Generation der Halbleitertechnologie die elektrischen Felder innerhalb der Transistoren. Dieses stärkere elektrische Feld stimuliert die Degradationsphänomene (Alterung der Transistoren, Selbsterhitzung, Rauschen, usw.), was zu einer immer stärkeren Degradation (Verschlechterung) der Transistoren führt. Daher erleiden die Transistoren in jeder neuen Technologiegeneration immer stärkere Verschlechterungen ihrer elektrischen Parameter. Um die Funktionalität und Zuverlässigkeit der Schaltung zu wahren, wird es daher unerlässlich, die Auswirkungen der geschwächten Transistoren auf die Schaltung präzise zu bestimmen. Die beiden wichtigsten Auswirkungen der Verschlechterungen sind ein verlangsamtes Schalten, sowie eine erhöhte Leistungsaufnahme der Schaltung. Bleiben diese Auswirkungen unberücksichtigt, kann die verlangsamte Schaltgeschwindigkeit zu Timing-Verletzungen führen (d.h. die Schaltung kann die Berechnung nicht rechtzeitig vor Beginn der nächsten Operation abschließen) und die Funktionalität der Schaltung beeinträchtigen (fehlerhafte Ausgabe, verfälschte Daten, usw.). Um diesen Verschlechterungen der Transistorparameter im Laufe der Zeit Rechnung zu tragen, werden Sicherheitstoleranzen eingeführt. So wird beispielsweise die Taktperiode der Schaltung künstlich verlängert, um ein langsameres Schaltverhalten zu tolerieren und somit Fehler zu vermeiden. Dies geht jedoch auf Kosten der Performanz, da eine längere Taktperiode eine niedrigere Taktfrequenz bedeutet. Die Ermittlung der richtigen Sicherheitstoleranz ist entscheidend. Wird die Sicherheitstoleranz zu klein bestimmt, führt dies in der Schaltung zu Fehlern, eine zu große Toleranz führt zu unnötigen Performanzseinbußen. Derzeit verlässt sich die Industrie bei der Zuverlässigkeitsbestimmung auf den schlimmstmöglichen Fall (maximal gealterter Schaltkreis, maximale Betriebstemperatur bei minimaler Spannung, ungünstigste Fertigung, etc.). Diese Annahme des schlimmsten Falls garantiert, dass der Chip (oder integrierte Schaltung) unter allen auftretenden Betriebsbedingungen funktionsfähig bleibt. Darüber hinaus ermöglicht die Betrachtung des schlimmsten Falles viele Vereinfachungen. Zum Beispiel muss die eigentliche Betriebstemperatur nicht bestimmt werden, sondern es kann einfach die schlimmstmögliche (sehr hohe) Betriebstemperatur angenommen werden. Leider lässt sich diese etablierte Praxis der Berücksichtigung des schlimmsten Falls (experimentell oder simulationsbasiert) nicht mehr aufrechterhalten. Diese Berücksichtigung bedingt solch harsche Betriebsbedingungen (maximale Temperatur, etc.) und Anforderungen (z.B. 25 Jahre Betrieb), dass die Transistoren unter den immer stärkeren elektrischen Felder enorme Verschlechterungen erleiden. Denn durch die Kombination an hoher Temperatur, Spannung und den steigenden elektrischen Feldern bei jeder Generation, nehmen die Degradationphänomene stetig zu. Das bedeutet, dass die unter dem schlimmsten Fall bestimmte Sicherheitstoleranz enorm pessimistisch ist und somit deutlich zu hoch ausfällt. Dieses Maß an Pessimismus führt zu erheblichen Performanzseinbußen, die unnötig und demnach vermeidbar sind. Während beispielsweise militärische Schaltungen 25 Jahre lang unter harschen Bedingungen arbeiten müssen, wird Unterhaltungselektronik bei niedrigeren Temperaturen betrieben und muss ihre Funktionalität nur für die Dauer der zweijährigen Garantie aufrechterhalten. Für letzteres können die Sicherheitstoleranzen also deutlich kleiner ausfallen, um die Performanz deutlich zu erhöhen, die zuvor im Namen der Zuverlässigkeit aufgegeben wurde. Diese Arbeit zielt darauf ab, maßgeschneiderte Sicherheitstoleranzen für die einzelnen Anwendungsszenarien einer Schaltung bereitzustellen. Für fordernde Umgebungen wie Weltraumanwendungen (wo eine Reparatur unmöglich ist) ist weiterhin der schlimmstmögliche Fall relevant. In den meisten Anwendungen, herrschen weniger harsche Betriebssbedingungen (z.B. sorgen Kühlsysteme für niedrigere Temperaturen). Hier können Sicherheitstoleranzen maßgeschneidert und anwendungsspezifisch bestimmt werden, sodass Verschlechterungen exakt toleriert werden können und somit die Zuverlässigkeit zu minimalen Kosten (Performanz, etc.) gewahrt wird. Leider sind die derzeitigen Standardentwurfswerkzeuge für diese anwendungsspezifische Bestimmung der Sicherheitstoleranz nicht gut gerüstet. Diese Arbeit zielt darauf ab, Standardentwurfswerkzeuge in die Lage zu versetzen, diesen Bedarf an Zuverlässigkeitsbestimmungen für beliebige Schaltungen unter beliebigen Betriebsbedingungen zu erfüllen. Zu diesem Zweck stellen wir unsere Forschungsbeiträge als vier Schritte auf dem Weg zu anwendungsspezifischen Sicherheitstoleranzen vor: Schritt 1 verbessert die Modellierung der Degradationsphänomene (Transistor-Alterung, -Selbsterhitzung, -Rauschen, etc.). Das Ziel von Schritt 1 ist es, ein umfassendes, einheitliches Modell für die Degradationsphänomene zu erstellen. Durch die Verwendung von materialwissenschaftlichen Defektmodellierungen werden die zugrundeliegenden physikalischen Prozesse der Degradationsphänomena modelliert, um ihre Wechselwirkungen zu berücksichtigen (z.B. Phänomen A kann Phänomen B beschleunigen) und ein einheitliches Modell für die simultane Modellierung verschiedener Phänomene zu erzeugen. Weiterhin werden die jüngst entdeckten Phänomene ebenfalls modelliert und berücksichtigt. In Summe, erlaubt dies eine genaue Degradationsmodellierung von Transistoren unter gleichzeitiger Berücksichtigung aller essenziellen Phänomene. Schritt 2 beschleunigt diese Degradationsmodelle von mehreren Minuten pro Transistor (Modelle der Physiker zielen auf Genauigkeit statt Performanz) auf wenige Millisekunden pro Transistor. Die Forschungsbeiträge dieser Dissertation beschleunigen die Modelle um ein Vielfaches, indem sie zuerst die Berechnungen so weit wie möglich vereinfachen (z.B. sind nur die Spitzenwerte der Degradation erforderlich und nicht alle Werte über einem zeitlichen Verlauf) und anschließend die Parallelität heutiger Computerhardware nutzen. Beide Ansätze erhöhen die Auswertungsgeschwindigkeit, ohne die Genauigkeit der Berechnung zu beeinflussen. In Schritt 3 werden diese beschleunigte Degradationsmodelle in die Standardwerkzeuge integriert. Die Standardwerkzeuge berücksichtigen derzeit nur die bestmöglichen, typischen und schlechtestmöglichen Standardzellen (digital) oder Transistoren (analog). Diese drei Typen von Zellen/Transistoren werden von der Foundry (Halbleiterhersteller) aufwendig experimentell bestimmt. Da nur diese drei Typen bestimmt werden, nehmen die Werkzeuge keine Zuverlässigkeitsbestimmung für eine spezifische Anwendung (Temperatur, Spannung, Aktivität) vor. Simulationen mit Degradationsmodellen ermöglichen eine Bestimmung für spezifische Anwendungen, jedoch muss diese Fähigkeit erst integriert werden. Diese Integration ist eines der Beiträge dieser Dissertation. Schritt 4 beschleunigt die Standardwerkzeuge. Digitale Schaltungsentwürfe, die nicht auf Standardzellen basieren, sowie komplexe analoge Schaltungen können derzeit nicht mit analogen Schaltungssimulatoren ausgewertet werden. Ihre Performanz reicht für solch umfangreiche Simulationen nicht aus. Diese Dissertation stellt Techniken vor, um diese Werkzeuge zu beschleunigen und somit diese umfangreichen Schaltungen simulieren zu können. Diese Forschungsbeiträge, die sich jeweils über mehrere Veröffentlichungen erstrecken, ermöglichen es Standardwerkzeugen, die Sicherheitstoleranz für kundenspezifische Anwendungsszenarien zu bestimmen. Für eine gegebene Schaltungslebensdauer, Temperatur, Spannung und Aktivität (Schaltverhalten durch Software-Applikationen) können die Auswirkungen der Transistordegradation ausgewertet werden und somit die erforderliche (weder unter- noch überschätzte) Sicherheitstoleranz bestimmt werden. Diese anwendungsspezifische Sicherheitstoleranz, garantiert die Zuverlässigkeit und Funktionalität der Schaltung für genau diese Anwendung bei minimalen Performanzeinbußen

    An assessment of the statistical distribution of Random Telegraph Noise Time Constants

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    As transistor sizes are downscaled, a single trapped charge has a larger impact on smaller devices and the Random Telegraph Noise (RTN) becomes increasingly important. To optimize circuit design, one needs assessing the impact of RTN on the circuit and this can only be accomplished if there is an accurate statistical model of RTN. The dynamic Monte Carlo modelling requires the statistical distribution functions of both the amplitude and the capture/emission time (CET) of traps. Early works were focused on the amplitude distribution and the experimental data of CETs were typically too limited to establish their statistical distribution reliably. In particular, the time window used has been often small, e.g. 10 sec or less, so that there are few data on slow traps. It is not known whether the CET distribution extracted from such a limited time window can be used to predict the RTN beyond the test time window. The objectives of this work are three fold: to provide the long term RTN data and use them to test the CET distributions proposed by early works; to propose a methodology for characterizing the CET distribution for a fabrication process efficiently; and, for the first time, to verify the long term prediction capability of a CET distribution beyond the time window used for its extraction

    Characterisation and modelling of Random Telegraph Noise in nanometre devices

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    The power consumption of digital circuits is proportional to the square of operation voltage and the demand for low power circuits reduces the operation voltage towards the threshold of MOSFETs. A weak voltage signal makes circuits vulnerable to noise and the optimization of circuit design requires an accurate noise model. RTN is the dominant noise for modern CMOS technologies. This research focuses on the instability induced by Random Telegraph Noise (RTN) in nano-devices for low power applications, such as the Internet of Things (IoT). RTN is a stochastic noise that can be observed in the drain/gate current of a device when traps capture and emit electrons or holes. The impact of RTN instabilities in devices has been widely investigated. Although progress has been made, the understanding of RTN instabilities remains incomplete and many issues are unresolved. This work focuses on developing a statistical model for characterising, modelling and analysing of the impact of RTN on MOSFET performance, as well as to study the prediction for long-term RTN impact on real circuits. As transistor sizes are downscaled, a single trapped charge has a larger impact and RTN becomes increasingly important. To optimize circuit design, one needs to assess the impact of RTN on circuits, which can only be accomplished if there is an accurate statistical model of RTN. The dynamic Monte Carlo modelling requires the statistical distribution functions of both the amplitude and the capture/emission time (CET) of traps. Early works were focused on the amplitude distribution and the experimental data of CETs has been too limited to establish their statistical distribution reliably. In particular, the time window used has often been small, e.g. 10 sec or less, so that there is little data on slow traps. It is not known whether the CET distribution extracted from such a limited time window can be used to predict the RTN beyond the test time window. The first contribution of this work is three-fold: to provide long-term RTN data and use it to test the CET distributions proposed by early works; to propose a methodology for characterising the CET distribution for a fabrication process efficiently; and, for the first time, to verify the long-term prediction capability of a CET distribution beyond the time window used for its extraction. On the statistical distributions of RTN amplitude, three different distributions were proposed by early works: Lognormal, Exponential, and Gumbel distributions. They give substantially different RTN predictions and agreement has not been reached on which distribution should be used, calling the modelling accuracy into question. The second contribution of this work is to assess the accuracy of these three distributions and to explore other distributions for better accuracy. A novel criterion has been proposed for selecting distributions, which requires a monotonic reduction of modelling errors with increasing number of traps. The three existing distributions do not meet this criterion and thirteen other distributions are explored. It is found that the Generalized Extreme Value (GEV) distribution has the lowest error and meets the new criterion. Moreover, to reduce modelling errors, early works used bimodal Lognormal and Exponential distributions, which have more fitting parameters. Their errors, however, are still higher than those of the monomodal GEV distribution. GEV has a long distribution tail and predicts substantially worse RTN impact. The project highlights the uncertainty in predicting the RTN distribution tail by different statistical models. The last contribution of the project is studying the impact of different gate biases on RTN distributions. At two different gate voltage conditions: one close to threshold voltage |Vth| and the other under operating conditions, it is found that the RTN amplitude follows different distributions. At operating voltage condition, Lognormal distribution has the lowest error for RTN amplitude distribution in comparison with other distributions. The amplitude distribution at close to |Vth| has a longer tail compared with the distribution tail at operating voltage. However, RTN capture/emission time distribution is not impacted by gate bias and follows Log-uniform distribution

    NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

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    Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the 15 accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process

    Experimental Characterization of Random Telegraph Noise and Hot Carrier Aging of Nano-scale MOSFETs

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    One of the emerging challenges in the scaling of MOSFETs is the reliability of ultra-thin gate dielectrics. Various sources can cause device aging, such as hot carrier aging (HCA), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and time dependent device breakdown (TDDB). Among them, hot carrier aging (HCA) has attracted much attention recently, because it is limiting the device lifetime. As the channel length of MOSFETs becomes smaller, the lateral electrical field increases and charge carriers become sufficiently energetic (“hot”) to cause damage to the device when they travel through the space charge region near the drain. Unlike aging that causes device parameters, such as threshold voltage, to drift in one direction, nano-scale devices also suffer from Random Telegraph Noise (RTN), where the current can fluctuate under fixed biases. RTN is caused by capturing/emitting charge carriers from/to the conduction channel. As the device sizes are reduced to the nano-meters, a single trap can cause substantial fluctuation in the current and threshold voltage. Although early works on HCA and RTN have improved the understanding, many issues remain unresolved and the aim of this project is to address these issues. The project is broadly divided into three parts: (i) an investigation on the HCA kinetics and how to predict HCA-induced device lifetime, (ii) a study of the interaction between HCA and RTN, and (iii) developing a new technique for directly measuring the RTN-induced jitter in the threshold voltage. To predict the device lifetime, a reliable aging kinetics is indispensable. Although early works show that HCA follows a power law, there are uncertainties in the extraction of the time exponent, making the prediction doubtful. A systematic experimental investigation was carried out in Chapter 4 and both the stress conditions and measurement parameters were carefully selected. It was found that the forward saturation current, commonly used in early work for monitoring HCA, leads to an overestimation of time exponents, because part of the damaged region is screened off by the space charges near the drain. Another source of errors comes from the inclusion of as-grown defects in the aging kinetics, which is not caused by aging. This leads to an underestimation of the time exponent. After correcting these errors, a reliable HCA kinetics is established and its predictive capability is demonstrated. There is confusion on how HCA and RTN interact and this is researched into in Chapter 5. The results show that for a device of average RTN, HCA only has a modest impact on RTN. RTN can either increase or decrease after HCA, depending on whether the local current under the RTN traps is rising or reducing. For a device of abnormally high RTN, RTN reduces substantially after HCA and the mechanism for this reduction is explored. The RTN-induced threshold voltage jitter, ∆Vth, is difficult to measure, as it is typically small and highly dynamic. Early works estimate this ∆Vth from the change in drain current and the accuracy of this estimation is not known. Chapter 6 focuses on developing a new ‘Trigger-When-Charged’ technique for directly measuring the RTN-induced ∆Vth. It will be shown that early works overestimate ∆Vth by a factor of two and the origin of this overestimation is investigated. This thesis consists of seven chapters. Chapter 1 introduces the project and its objectives. A literature review is given in Chapter 2. Chapter 3 covers the test facilities, measurement techniques, and devices used in this project. The main experimental results and analysis are given in Chapters 4-6, as described above. Finally, Chapter 7 concludes the project and discusses future works

    An Integral Methodology for Predicting Long Term RTN

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    Random Telegraph Noise (RTN) adversely impacts circuit performance and this impact increases for smaller devices and lower operation voltage. To optimize circuit design, many efforts have been made to model RTN. RTN is highly stochastic, with significant device-to-device variations. Early works often characterize individual traps first and then group them together to extract their statistical distributions. This bottom-up approach suffers from limitations in the number of traps it is possible to measure, especially for the capture and emission time constants, calling the reliability of extracted distributions into question. Several compact models have been proposed, but their ability to predict long term RTN is not verified. Many early works measured RTN only for tens of seconds, although a longer time window increases RTN by capturing slower traps. The aim of this work is to propose an integral methodology for modelling RTN and, for the first time, to verify its capability of predicting the long term RTN. Instead of characterizing properties of individual traps/devices, the RTN of multiple devices were integrated to form one dataset for extracting their statistical properties. This allows using the concept of effective charged traps (ECT) and transforms the need for time constant distribution to obtaining the kinetics of ECT, making long term RTN prediction similar to predicting ageing. The proposed methodology opens the way for assessing RTN impact within a window of 10 years by efficiently evaluating the probability of a device parameter at a given level

    Floating-Gate를 갖는 Flash Memory 소자의 신뢰성분석

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    학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 이종호.최근 NAND 플래시 메모리가 점차 고집적, 소형화 되면서 트랩에 전자가capture 또는 emission 되어 발생하는 Random Telegraph Noise (RTN)가 읽기 동작 및 소자의 불안정성 등 심각한 문제를 야기 시키고 있어 메모리 동작 시 중요한 사안으로 대두되고 있다. 또한, Interpoly dielectric (IPD)의 두께가 점점 감소함에 따라, IPD에 존재하는 트랩으로 인해 발생되는 신뢰성문제 또한 중요해지고 있다. 이에 본 논문에서는 Tunneling oxide및 IPD에 존재하는 트랩의 분석을 통해 Floating Gate NAND 플래시 메모리의 신뢰성에 대하여 논하고자 한다. 먼저, Read cell은 NAND string의 구조적인 특성으로 인해 pass cell들의 채널저항 영향을 받게 되며, 트랩의 위치와 에너지 준위를 추출함에 있어 pass cell들의 채널저항을 고려하여야 더욱 정확한 값을 추출할 수 있다는 것을 알 수 있었다. 또한, 최근 소자가 소형화 됨에 따라 인접 cell에 의한 간섭효과가 급속히 커지고 있기 때문에 인접 cell의 간섭효과에 따른 RTN 특성을 보고자 3-D TCAD 시뮬레이션 및 측정을 진행하였다. 인접 cell 상태에 따라, Read cell의 채널 Width 방향의 Electron current density 및 RTN에 의한 비트라인 전류변화, capture/emission time constant가 변화 됨을 3-D TCAD 시뮬레이션 및 측정을 통해 알 수 있었다. 또한, 앞서 pass cell들의 채널저항 효과 및 인접 cell 간섭효과를 이용하여 실제 32nm 및 26nm NAND 플래시 메모리string에서 RTN을 유발하는 트랩의 위치를 Vertical, Lateral, Width 방향으로 추출을 하여 3-D 그래프로 표현을 할 수 있었다. 더 나아가 NAND 플래시 메모리의 읽기 동작 시, RTN의 영향을 줄이기 위하여 ~μsec 범위의 pre-bias를 인가하는 새로운 읽기방법을 제안을 하였으며 측정을 통해 그 효과를 보여주었다. 다음으로는 NAND 플래시 메모리에서 발생하는 hysteresis 현상을 분석하기 위해 pulsed I-V 측정 및 비트라인 전류의 Transient 특성, 시뮬레이션을 진행하였으며, 이는 IPD의 bottom oxide에 존재하는 트랩에 의해 발생된다는 결론을 도출 할 수 있었다. 또한 이런 hysteresis 효과를 줄이기 위해 새로운 읽기방법을 제안을 하였으며 측정을 통해 그 효과를 보여주었다. 마지막 부록에서는 인접 cell 상태에 따라 영향을 받게 되는 간섭효과를 고려하여, 트랩 위치에 따른 비트라인 전류변화에 대한 모델링을 진행하였다. 모델링을 진행하기 위해 electric blockade length 및 트랩 위치가 고려된 Gaussian 형태를 가진 특성 함수를 정의를 하였고 이를 이용하여 트랩에 의한 비트라인 전류변화를 추출할 수 있었다. 3-D TCAD 시뮬레이션 결과와의 비교를 통해 제안된 모델이 매우 정확하다는 것을 알 수 있었고, 제안된 모델을 이용하면 트랩에 의한 비트라인 전류 변화값을 손쉽게 예측할 수 있을 것으로 예상된다.As flash memory cells continue to decrease in scale, random telegraph noise (RTN) caused by electron capture or emission at trap sites has become an important issue. Fluctuations in the threshold voltage (ΔVth) due to RTN can cause serious problems, such as read errors and device instability. As the thickness of the inter-poly dielectric IPD continues to decrease, the traps in the IPD also lead to reliability issues related to the leakage current and data retention. In this thesis, we investigate the reliability of NAND flash memory with respect to traps not only in the tunneling oxide but also in the IPD of the cell device. We first focus on traps that produce RTN in the tunneling oxide during a read operation. The trap position with respect to the channel surface and the floating-gate (xT) and the trap position along the channel length direction (yT) in the fabricated NAND flash memories were obtained by considering the channel resistance of the pass cells. The RTN in the floating-gate NAND flash cell strings interfered with the adjacent bit-line cell, and the effects of such on the fluctuations in the bit-line current (ΔIBL= high IBL – low IBL) were characterized. The electron current density (Je) of a read cell was found to be appreciably different depending on the position in the channel width direction relative to the interference produced by the adjacent bit-line cells. We verified that ΔIBL due to RTN increases as a high Je position is controlled to be close to a trap position in 32 nm NAND flash memory strings. The adjacent cell interference was shown to affect not only ΔIBL but also the ratio between the capture and the emission time constants [ln(τc/τe)]. We used the interference between the adjacent bit-lines (BLs) to obtain the trap position along the width direction and to represent the 3-D position of the traps in 32 nm and 26 nm NAND flash memory cells for the first time. We propose a new read method that reduces the effects on ΔIBL resulting from RTN. The pre-bias is controlled in the s range, and our method was confirmed to effectively suppress the effect of the RTN during read operations in NAND flash memory. Second of all, we investigate the hysteresis phenomenon in the floating-gate NAND flash memory strings, which originates from the traps in the bottom oxide of the oxide/nitride/oxide blocking dielectric (IPD). The hysteresis phenomenon in the floating-gate NAND flash memory strings is analyzed by measuring pulsed I-V and fast transient IBL. A new read method that suppresses the effect of the hysteresis phenomena was also proposed in order to reduce the read failures in NAND flash memory. In the Appendix, ΔIBL is modeled with the trap position as a parameter for the state (program or erase) of the adjacent bit-line cells, and it is observed to appreciably affect the current density distribution. ΔIBL is modeled by determining the integrated electron current density [J0=f(z)] and the electric blockade length (Lt) by considering the effect of the interference on the adjacent cells. A characteristic function [g(z)] with a Gaussian functional form is defined based on Lt and the trap position within the tunneling oxide from the channel surface (xT). Finally, ΔIBL is extracted by integrating f(z) and g(z). Our model accurately predicts ΔIBL, with the trap position as a parameter of the state of the bit-line cells, showing good agreement with data from a 3-D simulation.Abstract 1 Contents 4 Chapter 1 Introduction 7 1.1 RELIABILITY ISSUES IN NAND FLASH MEMORY 7 1.2 MOTIVATION AND ORGANIZATION 14 Chapter 2 Extraction of trap profiles considering channel resistance of pass cells 16 2.1 INTRODUCTION 16 2.2 DEVICE STRUCTURE AND MEASUREMENT METHOD 17 2.3 EQUATIONS OF TRAP PROFILES IN A NAND FLASH MEMORY STRING 19 2.4 VERIFICATION OF PROPOSED EQUATIONS 24 2.5 DISTRIBUTION OF TRAP POSITIONS IN TUNNELING OXIDE OF NAND FLASH MEMORY 29 Chapter 3 Effect of bit-line interference on RTN in NAND flash memory 30 3.1 INTRODUCTION 30 3.2 DEVICE STRUCTURE AND SIMULATION CONDITION 31 3.3 RESULTS OF 3-D TCAD SIMULATION 31 3.4 RTN MEASUREMENT RESULTS WITH THE STATE OF ADJACENT BIT-LINE CELLS 38 3.5 3-D TRAP POSITION IN TUNNELING OXIDE 45 Chapter 4 A new read method suppressing random telegraph noise 49 4.1 INTRODUCTION 49 4.2 DEVICE STRUCTURE AND MEASUREMENT SETUP 50 4.3 MEASUREMENT RESULTS AND DISCUSSION 52 Chapter 5 Hysteresis phenomena in floating-gate NAND flash memory 64 5.1 INTRODUCTION 64 5.2 DEVICE STRUCTURE AND MEASUREMENT SETUP 67 5.3 HYSTERESIS PHENOMENA IN ABNORMAL CELLS 69 5.4 ORIGIN OF HYSTERESIS PHENOMENON IN THE ABNORMAL CELL 76 5.5 HYSTERESIS PHENOMENA WITH BIAS AND P/E CYCLING STRESS 90 5.6 EFFECT OF HYSTERESIS PHENOMENA ON READ OPERATION 96 Conclusions 104 Appendix Modeling of ΔIBL due to RTN considering bit-line interference 106 A.1 INTRODUCTION 106 A.2 DEVICE STRUCTURE 108 A.3 RESULTS AND DISCUSSION 108 Bibliography 120 Abstract in Korean 129Docto
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