Electrical and Thermal Transport in Alternative Device Technologies

abstract: The goal of this research work is to develop a particle-based device simulator for modeling strained silicon devices. Two separate modules had to be developed for that purpose: A generic bulk Monte Carlo simulation code which in the long-time limit solves the Boltzmann transport equation for electrons; and an extension to this code that solves for the bulk properties of strained silicon. One scattering table is needed for conventional silicon, whereas, because of the strain breaking the symmetry of the system, three scattering tables are needed for modeling strained silicon material. Simulation results for the average drift velocity and the average electron energy are in close agreement with published data. A Monte Carlo device simulation tool has also been employed to integrate the effects of self-heating into device simulation for Silicon on Insulator devices. The effects of different types of materials for buried oxide layers have been studied. Sapphire, Aluminum Nitride (AlN), Silicon dioxide (SiO2) and Diamond have been used as target materials of interest in the analysis and the effects of varying insulator layer thickness have also been investigated. It was observed that although AlN exhibits the best isothermal behavior, diamond is the best choice when thermal effects are accounted for.Dissertation/ThesisM.S. Electrical Engineering 201

Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs

Non-conventional metal-oxide-semiconductor (MOS) devices have attracted researchers‟ attention for future ultra-large-scale-integration (ULSI) applications since the channel length of conventional MOS devices approached the physical limit. Among the non-conventional CMOS devices which are currently being pursued for the future ULSI, the fully-depleted (FD) SOI MOSFET is a serious contender as the SOI MOSFETs possess some unique features such as enhanced short-channel effects immunity, low substrate leakage current, and compatibility with the planar CMOS technology. However, due to the ultra-thin source and drain regions, FD SOI MOSFETs possess large series resistance which leads to the poor current drive capability of the device despite having excellent short-channel characteristics. To overcome this large series resistance problem, the source/drain area may be increased by extending S/D either upward or downward. Hence, elevated-source/drain (E-S/D) and recessed-source/drain (Re-S/D) are the two structures which can be used to minimize the series resistance problem. Due to the undesirable issues such as parasitic capacitance, current crowding effects, etc. with E-S/D structure, the Re-S/D structure is a better choice. The FD Re-S/D SOI MOSFET may be an attractive option for sub-45nm regime because of its low parasitic capacitances, reduced series resistance, high drive current, very high switching speed and compatibility with the planar CMOS technology. The present dissertation is to deal with the theoretical modeling and computer-based simulation of the FD SOI MOSFETs in general, and recessed source/drain (Re-S/D) ultra-thin-body (UTB) SOI MOSFETs in particular. The current drive capability of Re-S/D UTB SOI MOSFETs can be further improved by adopting the dual-metal-gate (DMG) structure in place of the conventional single-metal-gate-structure. However, it will be interesting to see how the presence of two metals as gate contact changes the subthreshold characteristics of the device. Hence, the effects of adopting DMG structure on the threshold voltage, subthreshold swing and leakage current of Re-S/D UTB SOI MOSFETs have been studied in this dissertation. Further, high-k dielectric materials are used in ultra-scaled MOS devices in order to cut down the quantum mechanical tunneling of carriers. However, a physically thick gate dielectric causes fringing field induced performance degradation. Therefore, the impact of high-k dielectric materials on subthreshold characteristics of Re-S/D SOI MOSFETs needs to be investigated. In this dissertation, various subthreshold characteristics of the device with high-k gate dielectric and metal gate electrode have been investigated in detail. Moreover, considering the variability problem of threshold voltage in ultra-scaled devices, the presence of a back-gate bias voltage may be useful for ultimate tuning of the threshold voltage and other characteristics. Hence, the impact of back-gate bias on the important subthreshold characteristics such as threshold voltage, subthreshold swing and leakage currents of Re-S/D UTB SOI MOSFETs has been thoroughly analyzed in this dissertation. The validity of the analytical models are verified by comparing model results with the numerical simulation results obtained from ATLAS™, a device simulator from SILVACO Inc

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Two-Dimensional Electronics - Prospects and Challenges

During the past 10 years, two-dimensional materials have found incredible attention in the scientific community. The first two-dimensional material studied in detail was graphene, and many groups explored its potential for electronic applications. Meanwhile, researchers have extended their work to two-dimensional materials beyond graphene. At present, several hundred of these materials are known and part of them is considered to be useful for electronic applications. Rapid progress has been made in research concerning two-dimensional electronics, and a variety of transistors of different two-dimensional materials, including graphene, transition metal dichalcogenides, e.g., MoS2 and WS2, and phosphorene, have been reported. Other areas where two-dimensional materials are considered promising are sensors, transparent electrodes, or displays, to name just a few. This Special Issue of Electronics is devoted to all aspects of two-dimensional materials for electronic applications, including material preparation and analysis, device fabrication and characterization, device physics, modeling and simulation, and circuits. The devices of interest include, but are not limited to transistors (both field-effect transistors and alternative transistor concepts), sensors, optoelectronics devices, MEMS and NEMS, and displays

Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

Towards New Generation Power MOSFETs for Automotive Electric Control Units

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are thought to be highly robust and versatile in high-speed switching applications in power electronics design due to its intrinsic high input impedance and compact size. This chapter concerns the development of a high-performance low voltage rating power MOSFET possessing low on-resistance and excellent avalanche current capability for an automotive electric power steering system (EPS). Using industry-standard Technology Computer-Aided Design (TCAD) tools, the planar- and trench-technology power MOSFETs, have been designed, modeled, simulated and compared. We surveyed and analyzed the specific on-resistance due to the different device structures, and various methods are highlighted and compared so that their benefits can be better understood and adopted. Additionally, the device ruggedness has been investigated and its improvement was evaluated and established for that of the trench MOSFET due to gate corner smoothing

Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields, including power electronics, illumination, and sensors. This reprint collects the 23 papers covering the full spectrum of the above applications and providing contributions from the on-going research at different levels, from materials to devices and from circuits to systems

Concept, design, simulation, and fabrication of an ultra-scalable vertical MOSFET

A new orientation to the conventional MOSFET is proposed. Processing issues, as well as short channel effects have been making planar MOSFET scaling increasingly difficult. It is predicted by the 2001 International Technology Roadmap for Semiconductors (ITRS) that non-planar devices will be needed for production as early as 2007. The device proposed in this thesis is similar in operation to the planar MOSFET, however the current transport from source to drain, normally in the same plane as the wafer surface, is oriented perpendicular to the die surface. The proposed device has successfully been simulated, showing a proof of concept. Fabrication of the proposed devices led to the creation of vertical MOS Gated Tunnel Diodes. This work, in fact, represents possibly the first demonstration of this type of technology. Suggestions are made to improve upon the proposed vertical MOSFET as well as the vertical MOS Gated Tunnel Diode

Study of Soi Annular Mosfet

Annular transistors are enclosed geometry transistors which reduce device leakage by eliminating diffusion edges. Due to the asymmetry of these devices with respect to inner and outer terminals; this study evaluates the behavior of the annular transistor with respect to both the inner and outer drain terminals. Along with this, the effects of geometry of the device on the leakage current and kink effects, related to the NMOS SOS devices at various temperatures are evaluated. Performance of NMOS annular transistor across four different transistor lengths (L= 1.3um, 1.4um 1.5um and 1.6um) are studied along with comparison to a NMOS rectilinear transistors (L=1.4um) at room temperature (RT) and 275C. The experimental results demonstrated a decrease in threshold voltage between the annular transistor with an inner drain compared to the rectilinear transistor by 20% at RT and 33% at 275C. Threshold voltage for an annular transistor with an inner drain is greater than the same transistor with an outer drain by 2% at RT and 3% at 275C. The Ion/Ioff ratio for annular devices with an inner drain compared to a rectangular device shows an improvement of 99% at both RT and 275C. The Ion/Ioff ratio for the same annular transistor with an inner drain verses an outer drain is greater by 75% at RT and 51% at 275C. The kink voltage for an annular transistor with an inner drain is greater than rectangular transistor by 2% at RT while 5% lower at 275C. Kink voltage for annular transistor with an outer drain is greater than the same transistor with an inner drain by 2% at RT and 1% at 275C. Early voltage (VA) for an annular transistor with an inner drain is greater than rectangular transistor by 22% at RT and 21% at 275C. VA for an annular transistor with an inner drain is greater than the same transistor with an outer drain by 22% at RT and 15% at 275C. Output resistance (rds) per unit width of an annular transistor with an inner drain is greater than rectilinear transistor by 77% at RT and 79% at 275C. rds for annular transistor with an inner drain is greater than that with an outer drain of the same device by 4% at RT and is lower by 25% at 275C. In conclusion when it is of the utmost importance to control leakage and device self gain annular transistors provide a significant improvement over the classical rectangular transistor. Some enhanced performance is observed when the inner contact is selected as the drain. It should also be noted that measurement accuracy precludes the taking of any conclusion where changes of less than 2% are observed.School of Electrical & Computer Engineerin

Temperature Dependent Analytical Modeling, Simulation and Characterizations of HEMTs in Gallium Nitride Process

Research is being conducted for a high-performance building block for high frequency and high temperature applications that combine lower costs with improved performance and manufacturability. Researchers have focused their attention on new semiconductor materials for use in device technology to address system improvements. Of the contenders, silicon carbide (SiC), gallium nitride (GaN), and diamond are emerging as the front-runners. GaN-based electronic devices, AlGaN/GaN heterojunction field effect transistors (HFETs), are the leading candidates for achieving ultra-high frequency and high-power amplifiers. Recent advances in device and amplifier performance support this claim. GaN is comparable to the other prominent material options for high-performance devices. The dissertation presents the work on analytical modeling and simulation of GaN high power HEMT and MOS gate HEMT, model verification with test data and device characterization at elevated temperatures. The model takes into account the carrier mobility, the doping densities, the saturation velocity, and the thickness of different layers. Considering the GaN material processing limitations and feedback from the simulation results, an application specific AlGaN/GaN RF power HEMT structure has been proposed. The doping concentrations and the thickness of various layers are selected to provide adequate channel charge density for the proposed devices. A good agreement between the analytical model, and the experimental data is demonstrated. The proposed temperature model can operate at higher voltages and shows stable operation of the devices at higher temperatures. The investigated temperature range is from 1000K to 6000K. The temperature models include the effect of temperature variation on the threshold voltage, carrier mobility, bandgap and saturation velocity. The calculated values of the critical parameters suggest that the proposed device can operate in the GHz range for temperature up to 6000K, which indicates that the device could survive in extreme environments. The models developed in this research will not only help the wide bandgap device researchers in the device behavioral study but will also provide valuable information for circuit designers