Room Temperature InP DFB Laser Array Directly Grown on (001) Silicon

Fully exploiting the silicon photonics platform requires a fundamentally new approach to realize high-performance laser sources that can be integrated directly using wafer-scale fabrication methods. Direct band gap III-V semiconductors allow efficient light generation but the large mismatch in lattice constant, thermal expansion and crystal polarity makes their epitaxial growth directly on silicon extremely complex. Here, using a selective area growth technique in confined regions, we surpass this fundamental limit and demonstrate an optically pumped InP-based distributed feedback (DFB) laser array grown on (001)-Silicon operating at room temperature and suitable for wavelength-division-multiplexing applications. The novel epitaxial technology suppresses threading dislocations and anti-phase boundaries to a less than 20nm thick layer not affecting the device performance. Using an in-plane laser cavity defined by standard top-down lithographic patterning together with a high yield and high uniformity provides scalability and a straightforward path towards cost-effective co-integration with photonic circuits and III-V FINFET logic

Colloidal quantum dots enabling coherent light sources for integrated silicon-nitride photonics

Integrated photoniccircuits, increasingly based on silicon (-nitride), are at the core of the next generation of low-cost, energy efficient optical devices ranging from on-chip interconnects to biosensors. One of the main bottlenecks in developing such components is that of implementing sufficient functionalities on the often passive backbone, such as light emission and amplification. A possible route is that of hybridization where a new material is combined with the existing framework to provide a desired functionality. Here, we present a detailed design flow for the hybridization of silicon nitride-based integrated photonic circuits with so-called colloidal quantum dots (QDs). QDs are nanometer sized pieces of semiconductor crystals obtained in a colloidal dispersion which are able to absorb, emit, and amplify light in a wide spectral region. Moreover, theycombine cost-effective solution based deposition methods, ambient stability, and low fabrication cost. Starting from the linear and nonlinear material properties obtained on the starting colloidal dispersions, we can predict and evaluate thin film and device performance, which we demonstrate through characterization of the first on-chip QD-based laser

Monolithic quantum-dot distributed feedback laser array on silicon

Electrically-pumped lasers directly grown on silicon are key devices interfacing silicon microelectronics and photonics. We report here, for the first time, an electrically-pumped, room-temperature, continuous-wave (CW) and single-mode distributed feedback (DFB) laser array fabricated in InAs/GaAs quantum-dot (QD) gain material epitaxially grown on silicon. CW threshold currents as low as 12 mA and single-mode side mode suppression ratios (SMSRs) as high as 50 dB have been achieved from individual devices in the array. The laser array, compatible with state-of-the-art coarse wavelength division multiplexing (CWDM) systems, has a well-aligned channel spacing of 20 0.2 nm and exhibits a record wavelength coverage range of 100 nm, the full span of the O-band. These results indicate that, for the first time, the performance of lasers epitaxially grown on silicon is elevated to a point approaching real-world CWDM applications, demonstrating the great potential of this technology

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Silicon Photonic Platforms and Systems for High-speed Communications

Data communication is a critical component of modern technology in our society. There is an increasing reliance on information being at our fingers tips and we expect a low-latency, high-bandwidth connection to deliver entertainment or enhanced productivity. In order to serve this demand, communications devices are being pressed for smaller form factors, higher data throughput, lower power consumption and lower cost. Similar demands exist in a number of applications including metro/long-haul telecommunications, shorter datacenter links and supercomputing. Silicon photonics promises to be a technology that will solve some of the difficulties with improving communication devices. Building photonics in silicon allows for reuse of the same fabrication technology that is used by the CMOS electronics industry, potentially allowing for large volumes, high yields and low costs. Part I of this thesis details the design of components needed in a high-speed silicon photonic platform to meet the current challenges for high-speed communications. The author’s work in modeling photodetectors resulted in improving photodetector bandwidth from 30 GHz to 67 GHz, the fastest reported at the time of publication. Details regarding the optimization and test of modulators are also presented with the first-reported 50 Gbps modulator at 1310-nm. A large scale parallel channel demonstration of high-speed silicon photonics is then presented showing the potential scalability for silicon photonics systems. A full transceiver requires a number of components other than the photodetector and modulator that are the core active pieces of a silicon photonics platform. Part II includes work on the design and test of silicon photonic components providing functionality beyond the photodetector and modulator. A novel design integrating Metal-Semiconductor Field Effect Transistors (MESFETs) into a silicon photonics platform without process change is shown. This integration enables enhanced control functionality with minimal overhead. The critical final piece for a silicon photonics platform, adding a light source, is demonstrated along with performance results of the resulting tunable, extended C-band laser. In Part III, previous work on an enhanced silicon photonics platform with complementary components is used to build a high-speed integrated coherent link and then tested with a silicon photonics-based tunable laser. The transceiver was shown to operate at 34 Gbaud dual-polarization 16-QAM for a total of 272 Gbps over a single channel. This was the first published demonstration of an integrated coherent where all of the optics were built in a silicon photonics platform

Wafer-level processing of ultralow-loss Si3N4

Photonic integrated circuits (PICs) are devices fabricated on a planar wafer that allow light generation, processing, and detection. Photonic integration brings important advantages for scaling up the complexity and functionality of photonic systems and facilitates their mass deployment in areas where large volumes and compact solutions are needed, e.g., optical interconnects. Among the material platforms available, silicon nitride (Si3N4) displays excellent optical properties such as broadband transparency, moderately high refractive index, and relatively strong nonlinearities. Indeed, Si3N4 integrated waveguides display ultralow-loss (few decibels per meter), which enables efficient light processing and nonlinear optics. Moreover, Si3N4 is compatible with standard complementary metal oxide semiconductor (CMOS) processing techniques,which facilitates the manufacture scalability required by mass deployment of PICs. However, the selection of a single photonic platform sets limitations to the device functionalities due to the intrinsic properties of the material and the fundamental limitation of optical waveguiding. Multilayer integration of different platforms can overcome the limitations encountered in a singleplatform PIC.This thesis presents the development of advanced techniques for the waferlevel manufacturing of ultralow-loss Si3N4 devices and approaches to enable their interface with active components like modulators and chip-scale comb sources (microcombs). The investigation covers the tailoring of a waveguide to the functionality required, the wafer-scale manufacturing of Si3N4, and how to overcome the limitations of a single platform on a wafer. These studies enable high-yield fabrication of microcombs, the integration of two Si3N4 platforms on the same wafer, and a strategy to efficiently couple to an integrated LiNbO3 layer to expand the chip functionality and scale up the complexity of the PIC

III-V-on-silicon photonic devices for optical communication and sensing

In the paper, we review our work on heterogeneous III-V-on-silicon photonic components and circuits for applications in optical communication and sensing. We elaborate on the integration strategy and describe a broad range of devices realized on this platform covering a wavelength range from 850 nm to 3.85 μm