160 research outputs found
Substrate Current Evaluation for Lightly and Heavily Doped MOSFETs at 45 Nm Process Using Physical Models
Substrate noise is a major integration issue in mixed signal circuits; particularly at radio frequency (RF) it becomes a key issue. In deep sub micron MOSFETs hot carrier effect induces device degradation. The impact ionization phenomenon is one of the main hot carrier effects. The paper covers the process and device level simulation of MOSFETs by TCAD and the substrate current comparison in lightly and heavily doped MOS. PMOS and NMOS devices are virtually fabricated with the help of ATHENA process simulator. The modeled devices include the hot carrier effects. The MOS devices are implemented on lightly and heavily doped substrates and substrate current is evaluated and compared with the help of ATLAS device simulator. Substrate current is better in lightly doped substrate than in heavily doped one. Drain current is also better in lightly doped than heavily doped substrates. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization
Substrate Current Evaluation for Lightly and Heavily Doped MOSFETs at 45 nm process Using Physical Models
Substrate noise is a major integration issue in mixed signal circuits; particularly at radio frequency (RF) it becomes a key issue. In deep sub micron MOSFETs hot carrier effect induces device degradation. The impact ionization phenomenon is one of the main hot carrier effects. The paper covers the process and device level simulation of MOSFETs by TCAD and the substrate current comparison in lightly and heavily doped MOS. PMOS and NMOS devices are virtually fabricated with the help of ATHENA process simulator. The modeled devices include the hot carrier effects. The MOS devices are implemented on lightly and heavily doped substrates and substrate current is evaluated and compared with the help of ATLAS device simulator. Substrate current is better in lightly doped substrate than in heavily doped one. Drain current is also better in lightly doped than heavily doped substrates. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization
Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics
The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity
Integrated Circuit Design in US High-Energy Physics
This whitepaper summarizes the status, plans, and challenges in the area of
integrated circuit design in the United States for future High Energy Physics
(HEP) experiments. It has been submitted to CPAD (Coordinating Panel for
Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the
Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US
Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to
June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the
whitepaper was distributed to the attendees before the workshop, the content
was discussed at the meeting, and this document is the resulting final product.
The scope of the whitepaper includes the following topics: Needs for IC
technologies to enable future experiments in the three HEP frontiers Energy,
Cosmic and Intensity Frontiers; Challenges in the different technology and
circuit design areas and the related R&D needs; Motivation for using different
fabrication technologies; Outlook of future technologies including 2.5D and 3D;
Survey of ICs used in current experiments and ICs targeted for approved or
proposed experiments; IC design at US institutes and recommendations for
collaboration in the future
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A substrate noise coupling model for lightly doped CMOS processes
This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks in the early stages of the design. The model scales with the size and separation of these blocks and it is validated with device simulations and with measurements on two different test chips. The effectiveness of different isolation techniques is investigated for lightly doped CMOS processes using device simulations and it is shown that P+ guard rings offer the best isolation, supppressing the noise by as much as 45dB when the guard rings are within a few microns
of the noise injector. Finally, the model is used to predict noise coupling between an inverter and an amplifier, with both circuit simulations and measurements on a chip fabricated in the TSMC 0.35Ecm CMOS process
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Substrate coupling macromodel for lightly doped CMOS processes
A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of device simulations or measurements. Once these parameters are known, the model can be used for any spacing between the injecting and sensing contacts and for different contact geometries. The model is validated with measurements for a lightly doped substrate with a buried layer and predicts the substrate resistance values to within 12%. The substrate resistances obtained using the model are also in close agreement with the three-dimensional simulations for a lightly doped substrate
Radiation effects studies for the high-resolution spectrograph
The generation and collection of charge carriers created during the passage of energetic protons through a silicon photodiode array are modeled. Pulse height distributions of noise charge collected during exposure of a digicon type diode array to 21 and 75 MeV protons were obtained. The magnitude of charge collected by a diode from each proton event is determined not only by diffusion, but by statistical considerations involving the ionization process itself. Utilizing analytical solutions to the diffusion equation for transport of minority carriers, together with the Vavilov theory of energy loss fluctuations in thin absorbers, simulations of the pulse height spectra which follow the experimental distributions fairly well are presented and an estimate for the minority carrier diffusion length L sub d is provided
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Automatic synthesis of analog layout : a survey
A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon
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