Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications

In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this work

Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs

The characteristic performance of n-type and p-type inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode, bulk Germanium FinFET device with 3-nm gate length (LG) are demonstrated by using 3-D quantum transport device simulation. The simulated bulk Ge FinFET device exhibits favorable short channel characteristics, including drain-induced barrier lowering (DIBL<10mV/V), sub threshold slope (SS∼64mV/dec.). Electron density distributions in ON-state and OFF-state also show that the simulated devices have large ION/IOFF ratios. Homogenous source/drain doping is maintained and only the channel doping is varied among different operating modes. Also, a constant threshold voltage |VTH|∼0.31V is maintained. Moreover, the calculated quantum capacitance (CQ) values of the Ge nanowire emphasizes the importance of quantum confinement effects (QCE) on the performance of the ultra-scaled devices

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <110> and <100> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90o on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5nm, 6nm, 7nm and 8nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions

Dopant metrology in advanced FinFETs

Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. This paper describes how, through correlation of experimental data with multimillion atom tight-binding simulations using the NEMO 3-D code, it is possible to identify the impurity's chemical species and determine their concentration, local electric field and depth below the Si/SiO$_{\mathrm{2}}$ interface. The ability to model the excited states rather than just the ground state is the critical component of the analysis and allows the demonstration of a new approach to atomistic impurity metrology.Comment: 6 pages, 3 figure