Hardware implantation of phased locked loop in biomedical diagnostics devices

Данная работа посвящена реализации синхронного демодулятора амплитудно-модулированных сигналов средствами цифровой обработки сигналов для повышения объема диагностической информации биомедицинских устройств. Особенностью реализуемого демодулятора является применение системы фазовой автоподстройки частоты (ФАПЧ), которая обеспечивая высокую чувствительность детектора, позволяет обрабатывать сигналы с малой мощностью. Для создания математической модели разрабатываемого демодулятора была составлена структурная схема ФАПЧ. При построении структурной схемы модели ФАПЧ, состоящая в данном случае из управляемого косинус-синусный генератора и петлевого фильтра учитывалось, что они работают в дискретном времени т. е. реализация этих схем будет выполнена полностью в цифровом виде. В результате расчета была получена передаточная характеристика и разностное уравнение петлевого фильтра (пропорционально-интегрирующего типа) для ФАПЧ второго порядка, а далее проведено имитационное моделирование рассчитанной системы ФАПЧ в приложении Simulink в пакете MatLab. Используя полученные формулы была написана программа для определения таких коэффициентов передачи петлевого фильтра, которые смогут обеспечить номинальную работу систему ФАПЧ. Полученные результаты имитационного моделирования подтвердили, что разработанный вариант петлевого фильтра обеспечивает широкую полосу захвата при одновременном подавлении дрожания фазы. Далее была составлена программа на языке Verilog c целью натурной реализации спроектированного демодулятора на основе программируемой логической интегральной схемы Xilinx серии Spartan 6 в системе проектирования Xilinx ISE. С целью верификации разработанного программного кода аппаратной реализации демодулятора в системе проектирования Xilinx ISE была проведена программная симуляцию входного сигналу в Testbench с одновременным использованием приложения ISIM, а визуализацию результатов симуляции - в GTKWave. Полученные экспериментальные результаты синтезированного демодулятора подтвердили результаты имитационного моделирования.This paper is devoted to the implementation of synchronous demodulator of amplitude-modulated signals by means of digital signal processing to increase the amount of diagnostic information of biomedical devices. A feature of the implemented demo-dulator is the usage of a phase-locked loop system, which, while ensuring high sensitivity of the demodulator, allows processing signals with low power. To create a mathematical model of the demodulator being developed, a phase-locked loop structure chart was drawn up. When drawing up a block diagram of the PLL model, which in this case consists of a numerically controlled cosine-sine oscillator and a loop filter, it was taken into account that they operate in discrete time, i. e. the implementation of these schemes will be performed entirely in digital form. As a result of the calculation, the transfer characteristic and difference equation of the loop filter (proportional-integrating type) for second-order of phase-locked loop were obtained, and then the simulation of the calculated phase-locked loop system was carried out in the Simulink application in MatLab. Using the formulas obtained, a program was written to determine such loop transfer coefficients that can ensure the nominal operation of the phase-locked loop. The obtained simulation results confirmed that the developed version of the loop filter provides a wide capture band while simultaneously suppressing phase jitter. At the next step, a computer program was compiled in the Verilog language with the purpose of the full-scale implementation of the designed demodulator based on the field-programmable gate arrayt debugging board such as Spartan 6 Xil-inx with the Xilinx ISE design system. In order to verify the developed software code for the hardware implementation of the demod-ulator in the Xilinx ISE design system, a software simulation of the input signal in Testbench with simultaneous use of the I SIM application was performed, and the simulation results were visualized in GTKWave. The obtained experimental results of the synthesized demodulator confirmed the results of simulation modeling

The Model of the Low Rate Telemetry Communication System for Matlab-Simulink

This article is dedicated to the model of low rate telemetry system, which has been developed for Matlab-Simulink environment. The purpose of this model is a research of the low rate telemetry transmission reliability in those cases where the modulation scheme carrier-subcarrier is used. This modulation scheme is widely used in case of the interplanetary spacecrafts. The main purpose of the model is a research of the effects of AWGN and phase noise especially for very low value of Eb/N0. Effects can be evaluated for the whole transmission system or for its components parts. The model described is very versatile and it can be easily modified or expanded

Analysis of Multipath Mitigation Techniques with Land Mobile Satellite Channel Model

Multipath is undesirable for Global Navigation Satellite System (GNSS) receivers, since the reception of multipath can create a significant distortion to the shape of the correlation function leading to an error in the receivers’ position estimate. Many multipath mitigation techniques exist in the literature to deal with the multipath propagation problem in the context of GNSS. The multipath studies in the literature are often based on optimistic assumptions, for example, assuming a static two-path channel or a fading channel with a Rayleigh or a Nakagami distribution. But, in reality, there are a lot of channel modeling issues, for example, satellite-to-user geometry, variable number of paths, variable path delays and gains, Non Line-Of-Sight (NLOS) path condition, receiver movements, etc. that are kept out of consideration when analyzing the performance of these techniques. Therefore, this is of utmost importance to analyze the performance of different multipath mitigation techniques in some realistic measurement-based channel models, for example, the Land Multipath is undesirable for Global Navigation Satellite System (GNSS) receivers, since the reception of multipath can create a significant distortion to the shape of the correlation function leading to an error in the receivers’ position estimate. Many multipath mitigation techniques exist in the literature to deal with the multipath propagation problem in the context of GNSS. The multipath studies in the literature are often based on optimistic assumptions, for example, assuming a static two-path channel or a fading channel with a Rayleigh or a Nakagami distribution. But, in reality, there are a lot of channel modeling issues, for example, satellite-to-user geometry, variable number of paths, variable path delays and gains, Non Line-Of-Sight (NLOS) path condition, receiver movements, etc. that are kept out of consideration when analyzing the performance of these techniques. Therefore, this is of utmost importance to analyze the performance of different multipath mitigation techniques in some realistic measurement-based channel models, for example, the Land Mobile Satellite (LMS) channel model [1]-[4], developed at the German Aerospace Center (DLR). The DLR LMS channel model is widely used for simulating the positioning accuracy of mobile satellite navigation receivers in urban outdoor scenarios. The main objective of this paper is to present a comprehensive analysis of some of the most promising techniques with the DLR LMS channel model in varying multipath scenarios. Four multipath mitigation techniques are chosen herein for performance comparison, namely, the narrow Early-Minus-Late (nEML), the High Resolution Correlator, the C/N0-based two stage delay tracking technique, and the Reduced Search Space Maximum Likelihood (RSSML) delay estimator. The first two techniques are the most popular and traditional ones used in nowadays GNSS receivers, whereas the later two techniques are comparatively new and are advanced techniques, recently proposed by the authors. In addition, the implementation of the RSSML is optimized here for a narrow-bandwidth receiver configuration in the sense that it now requires a significantly less number of correlators and memory than its original implementation. The simulation results show that the reduced-complexity RSSML achieves the best multipath mitigation performance in moderate-to-good carrier-to-noise density ratio with the DLR LMS channel model in varying multipath scenarios

A short survey on nonlinear models of the classic Costas loop: rigorous derivation and limitations of the classic analysis

Rigorous nonlinear analysis of the physical model of Costas loop --- a classic phase-locked loop (PLL) based circuit for carrier recovery, is a challenging task. Thus for its analysis, simplified mathematical models and numerical simulation are widely used. In this work a short survey on nonlinear models of the BPSK Costas loop, used for pre-design and post-design analysis, is presented. Their rigorous derivation and limitations of classic analysis are discussed. It is shown that the use of simplified mathematical models, and the application of non rigorous methods of analysis (e.g., simulation and linearization) may lead to wrong conclusions concerning the performance of the Costas loop physical model.Comment: Accepted to American Control Conference (ACC) 2015 (Chicago, USA

Delay Flip-Flop (DFF) Metastability Impact on Clock and Data Recovery (CDR) and Phase-Locked Loop (PLL) Circuits

Modeling delay flip-flops for binary (e.g., Alexander) phase detectors requires paying close attention to three important timing parameters: setup time, hold time, and clock edge-to-output (or briefly C2Q time). These parameters have a critical role in determining the status of the system on the circuit level. This study provided a guideline for designing an optimum DFF for an Alexander phase detector in a clock and data recovery circuit. Furthermore, it indicated DFF timing requirements for a high-speed phase detector in a clock and data recovery circuit. The CDR was also modeled by Verilog-A, and the results were compared with Simulink model achievements. Eventually designed in 45 nm CMOS technology, for 10 Gbps random sequence, the recovered clock contained 0.136 UI and 0.15 UI peak-to-peak jitter on the falling and rising edges respectively, and the lock time was 125 ns. The overall power dissipation was 21 mW from a 1 V supply voltage. Future work includes layout design and manufacturing of the proposed design

Simulation of optoelectronic oscillator injection locking, pulling and spiking phenomena

Complex envelope and reduced phase simulation models describing the dynamical behavior of an optoelectronic oscillator (OEO) under injection by an external source are described. The models are built on the foundations of a previously reported delay integral differential equation (DDE) theory of injection locking of time delay oscillators (TDO) such as the OEO. The DDE formulation is particularly amenable to high precision simulation using the Simulink block diagram environment. The correspondence between the blocks and the oscillator components offers intuition and considerable freedom to explore different circuit architectures and design variations with minimal coding effort. The simulations facilitate the study of the profound effect the multimode nature of a TDO has on its dynamical behavior. The reduced phase models that make use of the Leeson approximation are generally successful in reproducing the results of complex envelope models for established oscillations except for spiking phenomena for which the Leeson approximation fails. Simulation results demonstrating phenomena not captured by classical injection theory are presented, including multimode oscillation, the appearance of sidemodes in the RF and phase noise spectrum, and persistent spike trains redolent of recent experimental observations of 2pi phase pulse trains in a broadband OEO under injection

Modelling of 3-Phase p-q Theory-Based Dynamic Load for Real-Time Simulation

This article proposes a new method of modelling dynamic loads based on instantaneous p-q theory, to be employed in large powers system network simulations in a digital real-time environment. Due to the use of computationally heavy blocks such as phase-locked-loop (PLL), mean calculation,and coordinate transformation blocks (e.g., abc–dq0), real-time simulation of large networks with dynamic loads can be challenging. In order to decrease the computational burden associated to the dynamic load modelling, a p-q theory-based approach for load modelling is proposed in this paper. This approach is based on the well-known p-q instantaneous theory developed for power electronics converters, and it consists only of linear controllers and of a minimal usage of control loops, reducing the required computational power. This improves real-time performance and allows larger scale simulations. The introduced p-q theory-based load (PQL) model has been tested on standard networks implemented in a digital real time simulator, such as the SimBench semi-urban medium voltage network and the 118-bus Distribution System, showing significant improvement in terms of computational capability with respect to standard load models (e.g., MATLAB/Simulink dynamic load)