LC-VCO design optimization methodology based on the gm/ID ratio for nanometer CMOS technologies

In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier

Design of CMOS LC voltage controlled oscillators

This work presents the design and implementation of CMOS LC voltage controlled oscillators. On-chip planar spiral inductors and PMOS inversion mode varactors were utilized to implement the resonator. Two voltage controlled oscillators (VCOs) were realized as a part of this work, one designed to operate at 1.1 GHz while the second at 1.8 GHz. Both VCOs were implemented in a scalable digital CMOS process, with the former in a 1.5 micron CMOS process and the latter in a 0.5 micron technology. A simulation based methodology was adopted to arrive at a simple pi model used to model the metal and substrate related losses responsible for deteriorating the integrated inductor\u27s performance. Geometry based optimization techniques were utilized to arrive at an inductor geometry that ensures reasonable quality factor. In addition to the core VCO structure a host of test structures have been incorporated in order to carry out two-port network measurements in the future. Such measurements should enable one to gain a greater insight into the integrated inductor and varactor\u27s performance

Korkeataajuisten 65nm CMOS LC oscillaattoreiden käyttö kelojen hyvyysarvon todentamisessa

High quality factor inductors are essential for the design of low phase noise LC oscillators which play an important role in the transceivers of wireless communication devices. The reception capabilities of a radio frequency receiver are to great extent defined by the phase noise performance of the local oscillator. It is therefore important for modern single chip fully integrated transceiver design that high quality inductors are available and well modeled. In this work we investigate the possibility of evaluating the quality factor of an inductor by the phase noise it generates when used in a reference oscillator. A differential CMOS LC oscillator is designed for inductor test benching. The designed oscillator is fabricated on a 65nm CMOS process with two different inductor designs with simulated quality factors of 7.4 and 10.2. The overall combined silicon area of the two oscillators including inductors and probing pads is 680μm by 510μm. The oscillation frequencies are dictated by the designed inductors and were measured 3.04GHz and 4.56GHz. The oscillators achieve a phase noise of -125dBc/Hz and -124dBc/Hz at 1MHz offset with 14mW and 16mW power dissipation respectively. An oscillator phase noise model is fitted to the measured phase noise data of both oscillators and the model parameters are compared. The received quality factors for the designed inductors are 8.2 ± 0.8 and 10.8 ± 0.6 respectively. It was found that the measured phase noise is in good agreement with the results predicted by the model and the relative quality factor can, with certain limitations, be estimated through relative phase noise measurements

A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation

Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop accordingly to meet the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices. Specically this entails meeting stringent noise specications imposed by modern wireless standards, meeting low power consumption budgets to prolong battery lifetimes, operating under reduced supply voltages imposed by modern technology nodes and within the noisy environments of complex system-on-chip (SOC) designs, all in addition to consuming as little silicon area as possible. The ability of the PLL to achieve the above is thus key to its continual progress in enabling wireless technology achieve increasingly powerful products which increasingly benet our daily lives. This thesis furthers the development of PLLs with respect to meeting the challenges imposed upon it by modern wireless technology, in two ways. Firstly, the thesis describes in detail the advantages to be gained through employing a fully dierential PLL. Specically, such PLLs are shown to achieve low noise performance, consume less silicon area than their conventional counterparts whilst consuming similar power, and being better suited to the low supply voltages imposed by continual technology downsizing. Secondly, the thesis proposes a sub-banded VCO architecture which, in addition to satisfying simultaneous requirements for large tuning ranges and low phase noise, achieves signicant reductions in PLL loop bandwidth variation. First and foremost, this improves on the stability of the PLL in addition to improving its dynamic locking behaviour whilst oering further improvements in overall noise performance. Since the proposed sub-banded architecture requires no additional power over a conventional sub-banded architecture, the solution thus remains attractive to the realm of low power design. These two developments combine to form a fully dierential PLL with reduced loop bandwidth variation. As such, the resulting PLL is well suited to meeting the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices, and thus applicable to the continual development of wireless technology in benetting our daily lives

Design and implementation of fully integrated low-voltage low-noise CMOS VCO.

Yip Kim-fung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 95-100).Abstracts in English and Chinese.Abstract --- p.IAcknowledgement --- p.IIITable of Contents --- p.IVChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Objective --- p.6Chapter Chapter 2 --- Theory of Oscillators --- p.7Chapter 2.1 --- Oscillator Design --- p.7Chapter 2.1.1 --- Loop-Gain Method --- p.7Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10Chapter Chapter 3 --- Noise Analysis --- p.15Chapter 3.1 --- Origin of Noise Sources --- p.16Chapter 3.1.1 --- Flicker Noise --- p.16Chapter 3.1.2 --- Thermal Noise --- p.17Chapter 3.1.3 --- Noise Model of Varactor --- p.18Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19Chapter 3.2 --- Derivation of Resonator --- p.19Chapter 3.3 --- Phase Noise Model --- p.22Chapter 3.3.1 --- Leeson's Model --- p.23Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42Chapter 4.1 --- Device Modeling --- p.42Chapter 4.1.1 --- FET model --- p.42Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46Chapter 4.1.3 --- Planar Inductor --- p.48Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50Chapter 4.1.5 --- Inductor Layout Consideration --- p.54Chapter 4.1.6 --- CMOS RF Varactor --- p.55Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62Chapter 5.1.4 --- Output buffer --- p.63Chapter 5.1.5 --- Biasing Circuitry --- p.64Chapter 5.2 --- Spiral Inductor Design --- p.65Chapter 5.3 --- Determination of W/L ratio of FET --- p.67Chapter 5.4 --- Varactor Design --- p.68Chapter 5.5 --- Layout (Cadence) --- p.69Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74Chapter Chapter 6 --- Experimental Results and Discussion --- p.76Chapter 6.1 --- Measurement Setup --- p.76Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81Chapter 6.2.1 --- Output Spectrum --- p.81Chapter 6.2.2 --- Phase Noise Performance --- p.82Chapter 6.2.3 --- Tuning Characteristic --- p.83Chapter 6.2.4 --- Microphotograph --- p.84Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85Chapter 6.3.1 --- Output Spectrum --- p.85Chapter 6.3.2 --- Phase Noise Performance --- p.86Chapter 6.3.3 --- Tuning Characteristic --- p.87Chapter 6.3.4 --- Microphotograph --- p.88Chapter 6.4 --- Comparison of Measured Results --- p.89Chapter 6.4.1 --- Phase Noise Performance --- p.89Chapter 6.4.2 --- Tuning Characteristic --- p.90Chapter Chapter 7 --- Conclusion and Future Work --- p.93Chapter 7.1 --- Conclusion --- p.93Chapter 7.2 --- Future Work --- p.94References --- p.95Author's Publication --- p.100Appendix A --- p.101Appendix B --- p.104Appendix C --- p.10

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Above-IC RF MEMS devices for communication applications

Wireless communications are showing an explosive growth in emerging consumer and military applications of radiofrequency (RF), microwave, and millimeter-wave circuits and systems. Applications include wireless personal connectivity (Bluetooth), wireless local area networks (WLAN), mobile communication systems (GSM, GPRS, UMTS, CDMA), satellite communications and automotive electronics. Future cell phones and ground communication systems as well as communication satellites will require more and more sophisticated technologies. The increasing demand for size and weight reduction, cost savings, low power consumption, increased frequency and higher functionality and reconfigurability as part of multiband and multistandard operation is necessitating the use of highly integrated RF front-end circuits. Chip scaling has made a major contribution to this goal, but today a situation has been reached where the presence of numerous off-chip passive RF components imposes a critical bottleneck to further integration and miniaturization of wireless transceivers. Microelectromechanical systems (MEMS) technology is a rapidly emerging enabling technology that is intended to replace the discrete passives by their integrated counterparts. In this thesis, an original metal surface micromachining process, which is compatible with CMOS post-processing, for above-IC integration of RF MEMS tunable capacitors and suspended inductors is presented. A detailed study on SF6 inductively coupled plasma (ICP) releasing has been performed in order to ascertain the optimal process parameters. This study has emphasized the fact that temperature plays an important role in this process by limiting silicon dioxide etching. Moreover, the optimized recipe has been found to be independent of the sacrificial layer used (amorphous or polycrystalline silicon) and its thickness. Using this recipe, 15.6 µm/min Si underetch rate with high Si: SiO2 selectivity (> 20000: 1) has been obtained. Single-air-gap and double-air-gap parallel-plate MEMS tunable capacitors have been designed, fabricated and characterized in the pF range, from 1 MHz to 13.5 GHz. It has been shown that an optimized design of the suspended membrane and direct symmetrical current feed at both ports can significantly improve the quality factor and increase the self-resonant frequency, pushing it to 12 GHz and beyond. The maximum capacitance tuning range obtained for a single-air-gap capacitor is 29% for a bias voltage of 20 V. The maximum capacitance tuning range obtained for a double-air-gap capacitor is 207% for a bias voltage of 70 V. The post-processing of X-FAB BiCMOS wafers has been successfully demonstrated to fabricate monolithically integrated VCOs with above-IC MEMS LC tank. Comparing a suspended inductor and the X-FAB inductor with the same design, it has been shown that increasing the thickness of the spiral from 2.3 to 4 µm and having the spiral suspended 3 µm above the passivation layers lead to an improvement factor of 2 for the peak quality factor and a shift of the self-resonant frequency beyond 15 GHz. No significant variation on bipolar and MOS transistors characteristics due to the post-processing has been observed and we conclude that the variation due to post-processing is in the same range as the wafer-to-wafer variation. Based on our metal surface micromachining process, coplanar waveguide (CPW) MEMS shunt capacitive switches and variable true-time delay lines (V-TTDLs) have been designed, fabricated and characterized in the 1 - 20 GHz range. A novel MEMS device architecture: the SG-MOSFET, which combines a solid-state MOS transistor and a metal suspended gate has been proposed as DC current switch. The corresponding fabrication process using polysilicon as a sacrificial layer has been developed to release metal gate suspended over gate oxide by SF6 plasma. Very abrupt current switches have been demonstrated with subthreshold slope better than 10 mV/decade (better than the theoretical solid-state bulk or SOI MOSFET limit of 60 mV/decade) and ultra-low gate leakage (less than 0.001 pA/µm2) due to the air-gap

Analysis of the high frequency substrate noise effects on LC-VCOs

La integració de transceptors per comunicacions de radiofreqüència en CMOS pot quedar seriosament limitada per la interacció entre els seus blocs, arribant a desaconsellar la utilització de un únic dau de silici. El soroll d’alta freqüència generat per certs blocs, com l’amplificador de potencia, pot viatjar pel substrat i amenaçar el correcte funcionament de l’oscil·lador local. Trobem tres raons importants que mostren aquest risc d’interacció entre blocs i que justifiquen la necessitat d’un estudi profund per minimitzar-lo. Les característiques del substrat fan que el soroll d’alta freqüència es propagui m’és fàcilment que el de baixa freqüència. Per altra banda, les estructures de protecció perden eficiència a mesura que la freqüència augmenta. Finalment, el soroll d’alta freqüència que arriba a l’oscil·lador degrada al seu correcte comportament. El propòsit d’aquesta tesis és analitzar en profunditat la interacció entre el soroll d’alta freqüència que es propaga pel substrat i l’oscil·lador amb l’objectiu de poder predir, mitjançant un model, l’efecte que aquest soroll pot tenir sobre el correcte funcionament de l’oscil·lador. Es volen proporcionar diverses guies i normes a seguir que permeti als dissenyadors augmentar la robustesa dels oscil·ladors al soroll d’alta freqüència que viatja pel substrat. La investigació de l’efecte del soroll de substrat en oscil·ladors s’ha iniciat des d’un punt de vista empíric, per una banda, analitzant la propagació de senyals a través del substrat i avaluant l’eficiència d’estructures per bloquejar aquesta propagació, i per altra, determinant l’efecte d’un to present en el substrat en un oscil·lador. Aquesta investigació ha mostrat que la injecció d’un to d’alta freqüència en el substrat es pot propagar fins arribar a l’oscil·lador i que, a causa del ’pulling’ de freqüència, pot modular en freqüència la sortida de l’oscil·lador. A partir dels resultats de l’anàlisi empíric s’ha aportat un model matemàtic que permet predir l’efecte del soroll en l’oscil·lador. Aquest model té el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat. La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda. Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat. Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem. el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat. La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda. Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat. Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem.The integration of transceivers for RF communication in CMOS can be seriously limited by the interaction between their blocks, even advising against using a single silicon die. The high frequency noise generated by some of the blocks, like the power amplifier, can travel through the substrate, reaching the local oscillator and threatening its correct performance. Three important reasons can be stated that show the risk of the single die integration. Noise propagation is easier the higher the frequency. Moreover, the protection structures lose efficiency as the noise frequency increases. Finally, the high frequency noise that reaches the local oscillator degrades its performance. The purpose of this thesis is to deeply analyze the interaction between the high frequency substrate noise and the oscillator with the objective of being able to predict, thanks to a model, the effect that this noise may have over the correct behavior of the oscillator. We want to provide some guidelines to the designers to allow them to increase the robustness of the oscillator to high frequency substrate noise. The investigation of the effect of the high frequency substrate noise on oscillators has started from an empirical point of view, on one hand, analyzing the noise propagation through the substrate and evaluating the efficiency of some structures to block this propagation, and on the other hand, determining the effect on an oscillator of a high frequency noise tone present in the substrate. This investigation has shown that the injection of a high frequency tone in the substrate can reach the oscillator and, due to a frequency pulling effect, it can modulate in frequency the output of the oscillator. Based on the results obtained during the empirical analysis, a mathematical model to predict the effect of the substrate noise on the oscillator has been provided. The main advantage of this model is the fact that it is based on physical parameters of the oscillator and of the noise, allowing to determine the measures that a designer can take to increase the robustness of the oscillator as well as the consequences (trade-offs) that these measures have over its global performance. This model has been compared against both, simulations and real measurements, showing a very high accuracy to predict the effect of the high frequency substrate noise. The usefulness of the presented model as a design tool has been demonstrated in two case studies. Firstly, the conclusions obtained from the model have been applied in the design of an ultra low power consumption 2.5 GHz oscillator robust to the high frequency substrate noise with characteristics which make it compatible with the main communication standards in this frequency band. Finally, the model has been used as an analysis tool to evaluate the cause of the differences, in terms of performance degradation due to substrate noise, measured in two 60 GHz oscillators with two different tank inductor shielding strategies, floating and grounded. The model has determined that the robustness differences are caused by the improvement in the tank quality factor and in the oscillation amplitude and no by an increased isolation between the tank and the substrate. The model has shown to be valid and very accurate even in these extreme frequency range.Postprint (published version