Process-induced Structural Variability-aware Performance Optimization for Advanced Nanoscale Technologies

Department of Electrical EngineeringAs the CMOS technologies reach the nanometer regime through aggressive scaling, integrated circuits (ICs) encounter scaling impediments such as short channel effects (SCE) caused by reduced ability of gate control on the channel and line-edge roughness (LER) caused by limits of the photolithography technologies, leading to serious device parameter fluctuations and makes the circuit analysis difficult. In order to overcome scaling issues, multi-gate structures are introduced from the planar MOSFET to increase the gate controllability. The goal of this dissertation is to analyze structural variations induced by manufacturing process in advanced nanoscale devices and to optimize its impacts in terms of the circuit performances. If the structural variability occurs, aside from the endeavor to reduce the variability, the impact must be taken into account at the design level. Current compact model does not have device structural variation model and cannot capture the impact on the performance/power of the circuit. In this research, the impacts of structural variation in advanced nanoscale technology on the circuit level parameters are evaluated and utilized to find the optimal device shape and structure through technology computer-aided-design (TCAD) simulations. The detail description of this dissertation is as follows: Structural variation for nanoscale CMOS devices is investigated to extend the analysis approach to multi-gate devices. Simple and accurate modeling that analyzes non-rectilinear gate (NRG) CMOS transistors with a simplified trapezoidal approximation method is proposed. The electrical characteristics of the NRG gate, caused by LER, are approximated by a trapezoidal shape. The approximation is acquired by the length of the longest slice, the length of the smallest slice, and the weighting factor, instead of taking the summation of all the slices into account. The accuracy can even be improved by adopting the width-location-dependent factor (Weff). The positive effect of diffusion rounding at the transistor source side of CMOS is then discussed. The proposed simple layout method provides boosting the driving strength of logic gates and also saving the leakage power with a minimal area overhead. The method provides up to 13% speed up and also saves up to 10% leakage current in an inverter simulation by exploiting the diffusion rounding phenomena in the transistors. The performance impacts of the trapezoidal fin shape of a double-gate FinFET are then discussed. The impacts are analyzed with TCAD simulations and optimal trapezoidal angle range is proposed. Several performance metrics are evaluated to investigate the impact of the trapezoidal fin shape on the circuit operation. The simulations show that the driving capability improves, and the gate capacitance increases as the bottom fin width of the trapezoidal fin increases. The fan-out 4 (FO4) inverter and ring-oscillator (RO) delay results indicate that careful optimization of the trapezoidal angle can increase the speed of the circuit because the ratios of the current and capacitance have different impacts depending on the trapezoidal angle. Last but not least, the electrical characteristics of a double-gate-all-around (DGAA) transistor with an asymmetric channel width using device simulations are also investigated in this work. The DGAA FET, a kind of nanotube field-effect transistor (NTFET), can solve the problem of loss of gate controllability of the channel and provide improved short-channel behavior. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, this work proposes the n/p DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional GAA inverter structure. In the optimum structure, 27% propagation delay and 15% leakage power improvement can be achieved. Analysis and optimization for device-level variability are critical in integrated circuit designs of advanced technology nodes. Thus, the proposed methods in this dissertation will be helpful for understanding the relationship between device variability and circuit performance. The research for advanced nanoscale technologies through intensive TCAD simulations, such as FinFET and GAA, suggests the optimal device shape and structure. The results provide a possible solution to design high performance and low power circuits with minimal design overhead.ope

A New Method to Improve Accuracy of Leakage Current Estimation for Transistors with Non-Rectangular Gates due to Sub-wavelength Lithography Effects

Abstract−Non-ideal pattern transfer from drawn circuit layout to manufactured nanometer transistors can severely affect electrical characteristics such as drive current, leakage current, and threshold voltage. Obtaining accurate electrical models of non-rectangular transistors due to sub-wavelength lithography effects is indispensable for DFM-aware nanometer IC design. In this paper, TCAD device simulations are utilized to quantify the accuracy of a standard equivalent gate length extraction approach for non-rectangular transistors. It is verified that threshold voltage and current density are non-uniform along the channel width due to narrow-width related edge effects, leading to significant inaccuracy in the sub-threshold region. A new EGL extraction method utilizing location-dependent weighting factors and convex parameter extraction techniques is proposed to account for the current density non-uniformity. Preliminary results verified by TCAD simulations indicate that the accuracy of leakage current estimation for non-rectangular transistors can be significantly improved. The method is readily applicable to calibration with real silicon data

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots

Performance-Based Optical Proximity Correction

Ph.DDOCTOR OF PHILOSOPH

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Analytical and numerical modeling, fabrication and RF measurement techniques for RF planar micro-inductors on silicon

In mixed signal integrated circuits, the role of passives has become increasingly important. In particular, the characterization and implementation of an embedded planar coil inductor presents several challenges. The present work is a comprehensive study of micro inductors that includes analytical modeling, numerical simulation, in-house fabrication processes, circuit implementation in silicon, and RF measurement techniques. Although the inductor is widely integrated on silicon, there is still a need for closed form expressions for inductance and the quality factor. In addition, amongst the numerous commercially available simulation packages, there still is a need to identify the tool that best suits the design and implementation of micro-inductors on silicon. In this work, an analytical model is presented based on a desegmentation technique, which removes segments from a rectangular cavity to create the inductor coil geometry. Defining the Green\u27s function for each segment, the boundary conditions are applied to obtain a closed form expression for the Z matrix from which the inductance and Q have been obtained. For a numerical modeling, Ansoft\u27s High Frequency Structure Simulator (HFSS) is chosen as the preferred tool for an accurate and frequency dependent analysis. Several inductor geometrics have been modeled analytically and have been validated with HFSS where in each case there is excellent agreement. The model has also been successfully applied to irregularly shaped power planes that commonly occur in mixed signal circuits. The present work has established a fabrication process for micro-inductors using technologies available in the Semiconductor and Microsystems Fabrication Laboratory (SMFL) at RIT. A fabrication process has been developed to integrate inductors, transformers, capacitors, and PMOS (P-type Metal Oxide Semiconductor) transistors. Inductors and transformers have been made from copper and imbedded in a thick PECVD SiO₂ film. The process allows for an optional aluminum ground plane under the copper structures. Capacitors have been formed using the gate oxide as a dielectric and heavily doped silicon and aluminum as the electrodes. PMOS transistors have been implemented to control two varieties of LC tank circuits (parallel and series). The final contribution of the present work is establishing RF test methods for measuring inductance, and calculating the quality factor (Q). Experimental RF testing is performed using high frequency Cascade Microtech ground-signal-ground (GSG) probes and the 9100 probe station. Data has been captured using an Agilent 8363B network analyzer with a frequency range from 10 MHz to 40 GHz. A calibration procedure has been developed for a full two port measurement and a methodology has been optimized for measuring the impedance [Z] matrix and the scattering [S] matrix. The imput impedance is extracted from the [Z] matrix and Q has been calculated. There is excellent agreement between experimental results, numerical results from HFSS, and analytical results from the desegmentation technique

A memristive nanoparticle/organic hybrid synapstor for neuro-inspired computing

A large effort is devoted to the research of new computing paradigms associated to innovative nanotechnologies that should complement and/or propose alternative solutions to the classical Von Neumann/CMOS association. Among various propositions, Spiking Neural Network (SNN) seems a valid candidate. (i) In terms of functions, SNN using relative spike timing for information coding are deemed to be the most effective at taking inspiration from the brain to allow fast and efficient processing of information for complex tasks in recognition or classification. (ii) In terms of technology, SNN may be able to benefit the most from nanodevices, because SNN architectures are intrinsically tolerant to defective devices and performance variability. Here we demonstrate Spike-Timing-Dependent Plasticity (STDP), a basic and primordial learning function in the brain, with a new class of synapstor (synapse-transistor), called Nanoparticle Organic Memory Field Effect Transistor (NOMFET). We show that this learning function is obtained with a simple hybrid material made of the self-assembly of gold nanoparticles and organic semiconductor thin films. Beyond mimicking biological synapses, we also demonstrate how the shape of the applied spikes can tailor the STDP learning function. Moreover, the experiments and modeling show that this synapstor is a memristive device. Finally, these synapstors are successfully coupled with a CMOS platform emulating the pre- and post-synaptic neurons, and a behavioral macro-model is developed on usual device simulator.Comment: A single pdf file, with the full paper and the supplementary information; Adv. Func. Mater., on line Dec. 13 (2011

Computation lithography: Virtual reality and virtual virtuality

Computation lithography is enabled by a combination of physical understanding, mathematical abstraction, and implementation simplification. An application in the virtual world of computation lithography can be a virtual reality or a virtual virtuality depending on its engineering sensible-ness and technical feasibility. Examples under consideration include design-for- manufacturability and inverse lithography. © 2009 Optical Society of America.postprin