Analysis and mitigation of parallel-plate noise for high-isolation applications

Achieving highs levels of isolation between different functionalities in a PCB can be challenging. One of the major issues is that vertically adjacent planes or area fills in a PCB can form a parallel-plate waveguide with no cutoff frequency and serve as an efficient coupling mechanism between interconnects. Due to the finite size of the conductors, reflections off the edges of these parallel-plate cavities can result in the formation of standing-wave patterns with very high field strengths, resulting in high coupling at certain frequencies. This noise coupling mechanism can be suppressed by connecting the parallel plates together with an adequate amount of vias. However, adjacent power and ground conductors can not be conductively connected together because they are at different DC potentials. As a result, there is no way to eliminate the existence of parallel-plate noise in a power/ground cavity. A fundamental understanding of this problem is needed to determine how it can be mitigated. The first part of the thesis develops a qualitative understanding of the underlying physics of how noise is coupled to the parallel plates from a variety of interconnects and how the noise can spread throughout the design. This discussion is then expanded to more complex geometries that are representative of what could occur in actual designs. Test vehicles are created to study the noise coupling to various interconnects from noise injected into the power distribution network by an amplifier. Parameters affecting the transfer of noise from an amplifier to the power distribution network, such as the addition of capacitors, are then explored. An expression to predict the noise coupling using S-parameter measurements of the PCB and the amplifier is developed. It is demonstrated that results from full-wave electromagnetic simulation can be used to predict the amount of noise coupling before PCB fabrication. General design recommendations are then presented to improve design robustness to the parallel-plate noise --Abstract, page iii

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

Siirretty Doriast

Modeling and analysis of high-speed sources and serial links for signal integrity

As the computer and electronics industry moves towards higher data rates, signal integrity and electromagnetic interference (EMI) problems always present challenges for designers for high-speed data communication systems. To characterize the entire link path between transmitters and receivers, accurate models for sources, passive link path (such as traces, vias, connectors, etc), and terminations should be built before simulations either in frequency or time domain. Due to the imperfection of model, data corrections are preferred before time-domain simulations to ensure stability. Moreover, data obtained from models should be compared with measurement results to judge the level of agreement for validations. This thesis presents a new approach to model via structures to help design signal link path while maintaining a low insertion loss and minimizing crosstalk, borrowing the concepts from the transmission line theories. For the models of sources, a dipole model is proposed to represent integrated circuit (IC) radiation emissions while a circuit model for I/O current source is proposed for IC conductive emissions. Passivity and causality are two important properties for passive networks. This thesis also presents detailed algorithm to check passivity and causality for networks with arbitrary port numbers. Data corrections in term of passivity and causality enforcement are applied based on matrix perturbation theory. Last but not least, Feature Selective Validation (FSV) technique is expanded in this thesis to quantify the comparisons of data sets and provide quantitative standard for data optimization --Abstract, page iii

Performance and power optimization in VLSI physical design

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay

Fiber weave skew and copper roughness:effects on transmission line performance on PCB

Abstract. Designing manufacturable high performing transmission lines is an essential part of modern electronics design work. This thesis focuses on interconnect design and simulation while also examining how materials and manufacturing affects the designed interconnect. The goal of this work is to find how big and what kind of effects different design and manufacturing variables have and how to be mindful of all the relevant factors during the design phase. Specific focus areas are fiber weave effect and losses caused by copper roughness. In this thesis theory behind transmission lines on PCB is outlined first along with different material properties and relevant material test methods. Effects of different design parameters and material properties are then examined through simulations and literature. Accurate simulation of fiber weave skew with readily available simulation tools is difficult, but fiber weave skew itself can be mitigated with design choices. Copper roughness can be modelled with various models. Multiple different ways to represent copper roughness in the scope of PCB design exist. These various roughness representations are examined extensively through examples. Copper roughness was found to have significant effects on signal integrity and different roughness models were found to perform very differently.Lasipunosajoitusvääristymän ja kuparin karkeuden vaikutukset siirtolinjojen suorituskykyyn piirilevyllä. Tiivistelmä. Modernin elektroniikkasuunnittelun yksi keskeisistä osista on massatuotantokelpoisten korkean suorituskyvyn, siirtolinjojen suunnittelu. Tämä diplomityö keskittyy yhteyssuunnitteluun ja siirtolinjarakenteiden simulointiin piirilevyllä. Valmistusprosessien ja materiaalien vaikutuksia siirtolinjoihin tarkastellaan myös. Työn tavoitteena on selvittää Kuinka paljon ja millaisia vaikutuksia eri suunnittelu- ja materiaalivalinnoilla on sekä miten suunnittelija voi parhaiten ottaa eri seikat huomioon suunnittelun eri vaiheissa. Tarkemmin tarkasteltavat ilmiöt ovat kuparin pinnan karkeuden aiheuttamat häviöt ja piirilevyn eristemateriaalin lasikuitupunosrakenteen aiheuttama ajoitusvääristymä. Teoria piirilevyllä oleville siirtolinjoille on esitelty erilaisten materiaaliominaisuuksien ja materiaalien testausmenetelmien ohella ensin. Teoriaosuuden jälkeen eri suunnitteluparametrien ja materiaaliominaisuuksien vaikutuksia tutkitaan simulaatioiden ja kirjallisuuden pohjalta. Lasipunosajoitusvääristymän simulointi helposti saatavilla olevilla simulointityökaluilla on haasteellista, mutta ilmiön aiheuttamia vaikutuksia on mahdollista pienentää erilaisilla suunnitteluratkaisuilla. Kuparin karkeuden mallintamiseen on tarjolla useita erilaisia simulointimalleja. Lisäksi kuparin karkeus voidaan esittää usealla eri tavalla. Erilaisia kuparin karkeuden esitystapoja piirilevykontekstissa on tarkasteltu kattavasti esimerkkien kautta. Kuparin karkeuden todettiin vaikuttavan signaalien vaimentumiseen merkittävästi ja eri karkeusmallien huomattiin palauttavan huomattavasti toisistaan poikkeavia tuloksia

Modeling the Transcriptional Landscape of in vitro Neuronal Differentiation and ALS Disease

The spinal cord is a complex structure responsible for processing sensory inputs and motor outputs. As such, the developmental and spatial organization of cells is highly organized. Diseases affecting the spinal cord, such as Amyotrophic Lateral Sclerosis (ALS), result in the disruption of normal cellular function and intercellular interactions, culminating in neurodegeneration. Deciphering disease mechanisms requires a fundamental understanding of both the normal development of cells within the spinal cord as well as the homeostatic environment that allows for proper function. Biological processes such as cellular differentiation, maturation, and disease progression proceed in an asynchronous and cell type-specific manner. Until recently, bulk measurements of a mixed population of cells have been key in understanding these events. However, bulk measurements can obscure the molecular mechanisms involved in branched or coinciding processes, such as differential transcriptional responses occurring between subpopulations of cells. Measurements in individual cells have largely been restricted to 4 color immunofluorescence assays, which provide a solid but limited view of molecular-level changes. Recently, developments in single cell RNA-sequencing (scRNA-Seq) have provided an avenue of accurately profiling the RNA expression levels of thousands of genes concomitantly in an individual cell. With this increased experimental precision comes the ability to explore pathways that are differentially activated in subpopulations of cells, and to determine the transcriptional programs that underlie complex biological processes. In this dissertation, I will first review the key features of scRNA-Seq and downstream analysis. I will then discuss two applications of scRNA-seq: 1) the in vitro differentiation of mouse embryonic stem cells into motor neurons, and 2) the effect of the ALS-associated gene SOD1G93A expression on cultured motor neurons in a cellular model of ALS