Accurate and simple modeling of amplifier dc gain nonlinearity in switched-capacitor circuits

This paper presents an accurate and simple model for dc gain nonlinearity of operational amplifiers used in the switched-capacitor circuits such as the sigma-delta modulators. The proposed model can simply be used in the time-domain system level simulation of sigma-delta modulators to evaluate the effect of amplifier's dc gain nonlinearity on the overall linearity of the modulator as well as in the other switched- capacitor circuits as explored in the paper.Comisión Interministerial de Ciencia y Tecnología TIC2003-0235

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Modeling of switched-capacitor delta-sigma Modulators in SIMULINK

Precise behavioral modeling of switched-capacitor /spl Delta//spl Sigma/ modulators is presented. Considering noise (switches' and op-amps' thermal noise), clock jitter, nonidealities of integrators and op-amps including finite dc-gain (DCG) and unity gain bandwidth, slew-limiting, DCG nonlinearities and the input parasitic capacitance, quantizer hysteresis, switches' clock-feedthrough, and charge injection, exhaustive behavioral simulations that are close models of the transistor-level ones can be performed. The DCG nonlinearity of the integrators, which is not considered in many /spl Delta//spl Sigma/ modulators' modeling attempts, is analyzed, estimated, and modeled. It is shown that neglecting this parameter would lead to a significant underestimation of the modulators' behavior and increase the noise floor as well as the harmonic distortion at the output of the modulator. Evaluation and validation of the models were done via behavioral and transistor-level simulations for a second-order modulator using SIMULINK and HSPICE with a generic 0.35-/spl mu/m CMOS technology. The effects of the nonidealities and nonlinearities are clearly seen when compared to the ideal modulator in the behavioral and actual modulator in the circuit-level environment

Modeling OpAmp-induced harmonic distortion for switched-capacitor ΣΔ modulator design

This communication reports a new modeling of opamp-induced harmonic distortion in SC ΣΔ modulators, which is aimed to optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer of charge in a SC integrator and use power expansion and nonlinear fitting to obtain analytical models to represent harmonic distortion as function of the opamp finite gain-bandwidth (GB), slew-rate (SR) and nonlinear DC gain. Calculated models apply for all modulator architectures where harmonic distortion is dominated by the first integrator in the chain. We show that results provided by the new analytical models fit well to that obtained by simulation in time domain and have accuracy levels much larger than that provided by previously reported modeling approaches

Synthesis of Higher-Order K-Delta-1-Sigma Modulators for Wideband ADCs

As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents and device mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in nano-CMOS, the K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. This paper extends the KD1S to higher order topologies using a systematic synthesis procedure. Second and third order KD1S modulator are designed and simulated to demonstrate the synthesis method

Cascaded feedforward sigma-delta modulator for wide bandwidth applications

[[abstract]]A new sigma-delta modulator architecture for wide bandwidth application called cascaded feedforward sigma-delta modulator is proposed in this paper. This sigma-delta modulator is similar to the conventional feedforward summation sigma-delta modulator. The conventional feedforward summation sigma-delta modulator uses multi-bit feedback and therefore a multi-bit digital-to-analog converter (DAC) is needed. Due to the nonlinearity of the multi-bit DAC, it is difficult to be implemented. On the other hand the proposed approach uses 1.5-bit feedback, and thus the implementation of the analog part is much easier than the conventional one. Since the 1.5-bit feedback will cause coarse quantization errors, error cancellation must be done in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the signal to noise plus distortion ratio (SNDR) of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide bandwidth application.[[notice]]補正完

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110