1,555 research outputs found
Analysis and Design of High Speed Serial Interfaces for Automotive Applications
The demand for an enriched end-user experience and increased performance in next generation
electronic applications is never ending, and it is a common trend for a wide spectrum
of applications owing to different markets, like computing, mobile communication and automotive.
For this reason High Speed Serial Interface have become widespread components for
nowadays electronics with a constant demand for power reduction and data rate increase.
In the frame of gigabit serial systems, the work discussed in this thesis develops in two
directions: on one hand, the aim is to support the continuous data rate increase with the
development of novel link modeling approaches that will be employed for system level evaluation
and as support in the design and characterization phases. On the other hand, the
design considerations and challenges in the implementation of the transmitter, one of the
most delicate blocks for the signal integrity performance of the link, are central.
The first part of the activity regarding link performance predictions lead to the development
of an enhanced statistical simulation approach, capable to account for the transmitter
waveform shape in the ISI analysis, a characteristic that is missed by the available state-ofthe-
art simulation approaches. The proposed approach has been extensively tested by comparison
with traditional simulation approaches (Spice-like simulators) and validated against
experimental characterization of a test system, with satisfactory results.
The second part of the activity consists in the design of a high speed transmitter in a
deeply scaled CMOS technology, spanning from the concept of the circuit, its implementation
and characterization. Targets of the design are to achieve a data rate of 5 Gb/s with
a minimum voltage swing of 800 mV, thus doubling the data rate of the current transmitter
implementation, and reduce the power dissipation adopting a voltage mode architecture.
The experimental characterization of the fabricated lot draws a twofold picture, with some
of the performance figures showing a very good qualitative and quantitative agreement with
pre-silicon simulations, and others revealing a poor performance level, especially for the eye
diagram. Investigation of the root causes by the analysis of the physical silicon design, of the
bonding scheme of the prototypes and of the pre-silicon simulations is reported. Guidelines
for the redesign of the circuit are also given.Nel panorama delle applicazioni elettroniche il miglioramento delle performance di un prodotto
da una generazione alla successiva ha lo scopo di offrire all\u2019utilizzatore finale nuove
funzioni e migliorare quelle esistenti. Negli ultimi anni grazie al costante avanzamento della
tecnologia integrata, si \ue8 assistito ad un enorme sviluppo della capacit\ue0 computazionale dei
dispositivi in tutti i segmenti di mercato, quali ad esempio l\u2019information technology, la comunicazione
mobile e l\u2019automotive. La conseguente necessit\ue0 di mettere in comunicazione
dispostivi diversi all\u2019interno della stessa applicazione e di traferire grosse quantit\ue0 di dati ha
provocato una capillare diffusione delle interfacce seriali ad alta velocit\ue0, o High Speed Serial
Interfaces (HSSIs). La necessit\ue0 di ridurre il consumo di potenza e aumentare il bit rate per
questo tipo di applicazioni \ue8 diventata dunque un ambito di ricerca di estremo interesse.
Il lavoro discusso in questa tesi si colloca nell\u2019ambito della trasmissione di dati seriali a
bit rate superiori ad 1Gb/s e si sviluppa in due direzioni: da un lato, a sostegno del continuo
aumento del bit rate nelle nuove generazioni di interfacce, \ue8 stato affrontato lo sviluppo di
nuovi approcci di modellazione del sistema, che possano essere impiegati nella valutazione
delle prestazioni dell\u2019interfaccia e a supporto delle fasi di progettazione e di caratterizzazione.
Dall\u2019altro lato, si \ue8 focalizzata l\u2019attenzione sulle sfide e sulle problematiche inerenti il progetto
di uno dei blocchi pi\uf9 delicati per le prestazioni del sistema, il trasmettitore.
La prima parte della tesi ha come oggetto lo sviluppo di un approccio di simulazione
statistico innovativo, in grado di includere nell\u2019analisi degli effetti dell\u2019interferenza di intersimbolo
anche la forma d\u2019onda prodotta all\u2019uscita del trasmettitore, una caratteristica che
non \ue8 presente in altri approcci di simulazione proposti in letteratura. La tecnica proposta
\ue8 ampiamente testata mediante il confronto con approcci di simulazione tradizionali (di tipo
Spice) e mediante il confronto con la caratterizzazione sperimentale di un sistema di test, con
risultati pienamente soddisfacenti.
La seconda parte dell\u2019attivit\ue0 riguarda il progetto di un trasmettitore integrato high speed
in tecnologia CMOS a 40nm e si estende dallo studio di fattibilit\ue0 del circuito fino alla sua
realizzazione e caratterizzazione. Gli obiettivi riguardano il raggiungimento di un bit rate
pari a 5 Gb/s, raddoppiando cos\uec il bit rate dell\u2019attuale implementazione, e di una tensione
differenziale di uscita minima di 800mV (picco-picco) riducendo allo stesso tempo la potenza
dissipata mediante l\u2019adozione di una architettura Voltage Mode. I risultati sperimentali
ottenuti dal primo lotto fabbricato non delineano un quadro univoco: alcune performance
mostrano un ottimo accordo qualitativo e quantitativo con le simulazioni pre-fabbricazione,
mentre prestazioni non soddisfacenti sono state ottenute in particolare per il diagramma ad
occhio. Grazie all\u2019analisi del layout del prototipo, del bonding tra silicio e package e delle
simulazioni pre-fabbricazione \ue8 stato possibile risalire ai fattori responsabili del degrado delle
prestazioni rispetto alla previsioni pre-fabbricazione, permettendo inoltre di delineare le
linee guida da seguire nella futura progettazione di un nuovo prototipo
Analog-Digital System Modeling for Electromagnetic Susceptibility Prediction
The thesis is focused on the noise susceptibility of communication networks. These analog-mixed signal systems operate in an electrically noisy environment, in presence of multiple equipments connected by means of long wiring. Every module communicates using a transceiver as an interface between the local digital signaling and the data transmission through the network. Hence, the performance of the IC transceiver when affected by disturbances is one of the main factors that guarantees the EM immunity of the whole equipment. The susceptibility to RF and transient disturbances is addressed at component level on a CAN transceiver as a test case, highlighting the IC features critical for noise immunity.
A novel procedure is proposed for the IC modeling for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling IC ports with a physical circuit and the internal links with a behavioural block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of non-linear device switching behaviours. The effectiveness of the modeling process is verified by applying the proposed technique to a CAN transceiver, involved in a real immunity test on a data communication link. The obtained model is successfully implemented in a commercial solver to predict both the functional signals and the RF noise immunity at component level.
The noise immunity at system level is then evaluated on a complete communication network, analyzing the results of several tests on a realistic CAN bus. After developing models for wires and injection probes, a noise immunity test in avionic environment is carried out in a simulation environment, observing good overall accuracy and efficiency
Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers
Over the past few decades, incessant growth of Internet networking traffic and High-Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends have enabled the semiconductor and microelectronic industry to dramatically scale the bandwidth of high-loss interfaces such as Ethernet, backplane, and Digital Subscriber Line (DSL). The key to achieving higher bandwidth is to employ equalization technique to compensate the channel impairments such as Inter-Symbol Interference (ISI), crosstalk, and environmental noise. Therefore, todayâs advanced input/outputs (I/Os) has been equipped with sophisticated equalization techniques to push beyond the uncompensated bandwidth of the system. To this end, process scaling has continually increased the data processing capability and improved the I/O performance over the last 15 years. However, since the channel bandwidth has not scaled with the same pace, the required signal processing and equalization circuitry becomes more and more complicated. Thereby, the energy efficiency improvements are largely offset by the energy needed to compensate channel impairments. In this design paradigm, re-thinking about the design strategies in order to not only satisfy the bandwidth performance, but also to improve power-performance becomes an important necessity. It is well known in communication theory that coding and signaling schemes have the potential to provide superior performance over band-limited channels. However, the choice of the optimum data communication algorithm should be considered by accounting for the circuit level power-performance trade-offs. In this thesis we have investigated the application of new algorithm and signaling schemes in wireline communications, especially for communication between microprocessors, memories, and peripherals. A new hybrid NRZ/Multi-Tone (NRZ/MT) signaling method has been developed during the course of this research. The system-level and circuit-level analysis, design, and implementation of the proposed signaling method has been performed in the frame of this work, and the silicon measurement results have proved the efficiency and the robustness of the proposed signaling methodology for wireline interfaces. In the first part of this work, a 7.5 Gb/s hybrid NRZ/MT transceiver (TRX) for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel bearing 45 dB loss at 2.5 GHz. The measurement results of the first prototype confirm that NRZ/MT serial data TRX can offer an energy-efficient solution for MDB memory interfaces. Motivated by the satisfying results of the first prototype, in the second phase of this research we have exploited the properties of multi-tone signaling, especially orthogonality among different sub-bands, to reduce the effect of crosstalk in high-dense wireline interconnects. A four-channel transceiver has been implemented in a standard CMOS 40 nm technology in order to demonstrate the performance of NRZ/MT signaling in presence of high channel loss and strong crosstalk noise. The proposed system achieves 1 pJ/bit power efficiency, while communicating over a MDB memory channel at 36 Gb/s aggregate data rate
Cellular Underwater Wireless Optical CDMA Network: Potentials and Challenges
Underwater wireless optical communications is an emerging solution to the
expanding demand for broadband links in oceans and seas. In this paper, a
cellular underwater wireless optical code division multiple-access (UW-OCDMA)
network is proposed to provide broadband links for commercial and military
applications. The optical orthogonal codes (OOC) are employed as signature
codes of underwater mobile users. Fundamental key aspects of the network such
as its backhaul architecture, its potential applications and its design
challenges are presented. In particular, the proposed network is used as
infrastructure of centralized, decentralized and relay-assisted underwater
sensor networks for high-speed real-time monitoring. Furthermore, a promising
underwater localization and positioning scheme based on this cellular network
is presented. Finally, probable design challenges such as cell edge coverage,
blockage avoidance, power control and increasing the network capacity are
addressed.Comment: 11 pages, 10 figure
A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications
We describe an effcient system-level simulator that, starting from the architecture of a well-specified transmissive medium (a channel modelled as single-ended or coupled differential microstrips plus cables) and including the system-level characteristics of transmitter and receiver (voltage swing, impedance, etc.), computes the eye diagram and the bit-error rate that is obtained in high-speed serial interfaces. Various equalization techniques are included, such as feed-forward equalization at the transmitter, continuous-time linear equalization and decision-feedback equalization at the receiver. The impact of clock and data jitter on the overall system performance can easily be taken into account and fully-adaptive equalization can be simulated without increasing the computational burden or the model\u2019s complexity
MONet: Heterogeneous Memory over Optical Network for Large-Scale Data Centre Resource Disaggregation
Memory over Optical Network (MONet) system is a disaggregated data center architecture where serial (HMC) / parallel (DDR4) memory resources can be accessed over optically switched interconnects within and between racks. An FPGA/ASIC-based custom hardware IP (ReMAT) supports heterogeneous memory pools, accommodates optical-to-electrical conversion for remote access, performs the required serial/parallel conversion and hosts the necessary local memory controller. Optically interconnected HMC-based (serial I/O type) memory card is accessed by a memory controller embedded in the compute card, simplifying the hardware near the memory modules. This substantially reduces overheads on latency, cost, power consumption and space. We characterize CPU-memory performance, by experimentally demonstrating the impact of distance, number of switching hops, transceivers, channel bonding and bit-rate per transceiver on bit-error rate, power consumption, additional latency, sustained remote memory bandwidth/throughput (using industry standard benchmark STREAMS) and cloud workload performance (such as operations per second, average added latency and retired instructions per second on memcached with YCSB cloud workloads). MONet pushes the CPU-memory operational limit from a few centimetres to 10s of metres, yet applications can experience as low as 10% performance penalty (at 36m) compared to a direct-attached equivalent. Using the proposed parallel topology, a system can support up to 100,000 disaggregated cards
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