1,733 research outputs found
Stepwise Design Methodology and Heterogeneous Integration Routine of Air-Cooled SiC Inverter for Electric Vehicle
Carrying on SiC devices, the air-cooled inverter of the electric vehicle (EV) can eliminate the traditional complicated liquid-cooling system in order to obtain a light and compact performance of the powertrain, which is considered as the trend of next-generation EV. However, the air-cooled SiC inverter lacks strategic design methodology and heterogeneous integration routine for critical components. In this article, a stepwise design methodology is proposed for the air-cooled SiC inverter in the power module, dc-link capacitor, and heat sink levels. In the power module level, an electrical-thermal-mechanical multiphysics model is proposed. The multidimension stress distribution principles in a six-in-one SiC power module are demonstrated. An improved power module is presented and confirmed by using the observed multiphysics design principles. In the dc-link capacitor level, ripple modeling of the inverter and capacitor are created. Considering the tradeoffs among ripple voltage, ripple current, and cost, optimal strategies to determine the material and minimize the capacitance of the dc-link capacitor are proposed. In the heat sink level, thermal resistance of air-cooled heat sink is modeled. Structure and material properties of the heat sink are optimally designed by using a comprehensive electro-thermal analysis. Based on the optimal design results, the prototypes of the customized SiC power module and heterogeneously integrated air-cooled inverter are fabricated. Experimental results are presented to demonstrate the feasibility of the designed and manufactured air-cooled SiC inverter.Ministry of Education (MOE)Nanyang Technological UniversityThis work was supported in part by the National Natural Science Foundation of China under Grant 51607016, in part by the National Key Research and Development Program of China under Grant 2017YFB0102303, and in part by the Singapore ACRF Tier 1 Grant RG 85/18. The work of X. Zhang was supported by the NTU Startup Grant (SCOPES)
Post Developmental Applications of Analog-to-Digital Converters
The goal of this project is to improve upon the post-development applications for analog-to-digital converters (ADC). Specifically, three tasks were pursued throughout the duration of this project: The first focused on the development of an improved, low jitter evaluation board for the AD7626 ADC. The second task focused on the generation of a process by which Analog Devices can create in-house input/output buffer information specification (IBIS) models. Finally, the third task involved assessing the feasibility of integrating Analog Devices\u27 products with third party microcontrollers
Condition Monitoring of Power Electronic Systems through Data Analysis of Measurement Signals and Control Output Variables
A major disadvantage of existing condition monitoring methods is the need for additional sensors and measuring equipment. In this work, this disadvantage is eliminated by completely avoiding additional hardware. Instead, software-based methods from the field of machine learning are used. Therefore, measurement signals and control output variables are utilized which are acquired and processed in any power electronic system for the purpose of converter control. The publication focuses on two main converter components: power semiconductors and DC link capacitor. For each component, the aging mechanisms that have been studied in the literature are explained. Based on the aging mechanisms, the degradation indicators are identified. Then, a converter model is built that allows the variation of degradation indicators in order to analyze their effects on the available data set. These findings form the basis for mathematical models, which detect future failure mechanisms of this type during converter operation. The test setup must offer the possibility of generating reproducible failure cases in various components with the aid of additional failure equipment. Finally, failure mechanisms are intentionally introduced at the test bench in order to validate the methodology of the developed approach
Health Condition Monitoring and Fault-Tolerant Operation of Adjustable Speed Drives
Adjustable speed drives (ASDs) have been extensively used in industrial applications over the past few decades because of their benefits of energy saving and control flexibilities. However, the wider penetration of ASD systems into industrial applications is hindered by the lack of health monitoring and fault-tolerant operation techniques, especially in safety-critical applications. In this dissertation, a comprehensive portfolio of health condition monitoring and fault-tolerant operation strategies is developed and implemented for multilevel neutral-point-clamped (NPC) power converters in ASDs. Simulations and experiments show that these techniques can improve power cycling lifetime of power transistors, on-line diagnosis of switch faults, and fault-tolerant capabilities.The first contribution of this dissertation is the development of a lifetime improvement Pulse Width Modulation (PWM) method which can significantly extend the power cycling lifetime of Insulated Gate Bipolar Transistors (IGBTs) in NPC inverters operating at low frequencies. This PWM method is achieved by injecting a zero-sequence signal with a frequency higher than that of the IGBT junction-to-case thermal time constants. This, in turn, lowers IGBT junction temperatures at low output frequencies. Thermal models, simulation and experimental verifications are carried out to confirm the effectiveness of this PWM method. As a second contribution of this dissertation, a novel on-line diagnostic method is developed for electronic switch faults in power converters. Targeted at three-level NPC converters, this diagnostic method can diagnose any IGBT faults by utilizing the information on the dc-bus neutral-point current and switching states. This diagnostic method only requires one additional current sensor for sensing the neutral-point current. Simulation and experimental results verified the efficacy of this diagnostic method.The third contribution consists of the development and implementation of a fault-tolerant topology for T-Type NPC power converters. In this fault-tolerant topology, one additional phase leg is added to the original T-Type NPC converter. In addition to providing a fault-tolerant solution to certain switch faults in the converter, this fault-tolerant topology can share the overload current with the original phase legs, thus increasing the overload capabilities of the power converters. A lab-scale 30-kVA ASD based on this proposed topology is implemented and the experimental results verified its benefits
Recommended from our members
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices
Modeling and Control of a 7-Level Switched Capacitor Rectifier for Wireless Power Transfer Systems
Wireless power continues to increase in popularity for consumer device charging. Rectifier characteristics like efficiency, compactness, impedance tunability, and harmonic content make the multi-level switched capacitor rectifier (MSC) an exceptional candidate for modern WPT systems. The MSC shares the voltage conversion characteristics of a post-rectification buck-boost topology, reduces waveform distortion via its multi-level modulation scheme, demonstrates tank tunability via the phase control inherent to actively switched rectifiers, and accomplishes all this without a bulky filter inductor. In this work, the MSC WPT system operation is explained, and a loss model is constructed. A prototype system is used to validate the models, showing exceptional agreement with the predicted efficiencies. The modeled MSC efficiencies are between 96.1% and 98.0% over the experimental power range up to 20.0 W.
Two significant control loops are required for the MSC to be implemented in a real system. First, the output power is regulated using the modulation of the rectifier\u27s input voltage. Second, the switching frequency of the rectifier must exactly match the WPT carrier frequency set by the inverter on the primary side. Here, a small signal discrete time model is used to construct four transfer functions relating to the output voltage. Then, four novel time-to-time transfer functions are built on top of the discrete time model to inform the frequency synchronization feedback loop. Both loops are tested and validated in isolation. Finally, the dual-loop control problem is defined, closed form equations that include loop interactions are derived, and stable wide-range dual-loop operation is demonstrated experimentally
- …