MADES: A SysML/MARTE high level methodology for real-time and embedded systems

International audienceRapid evolution of real-time and embedded systems (RTES) is continuing at an increasing rate, and new method-ologies and design tools are needed to reduce design complexity while decreasing development costs and integrating aspects such as verification and validation. Model-Driven Engineering offers an interesting solution to the above mentioned challenges and is being widely used in various industrial and academic research projects. This paper presents the EU funded MADES project which aims to develop novel model-driven techniques to improve existing practices in development of RTES for avionics and surveillance embedded systems industries. MADES proposes a subset of existing UML profiles for embedded systems modeling: namely MARTE and SysML, and is developing new tools and technologies that support design, validation, simulation and eventual automatic code generation, while integrating aspects such as component re-use. In this paper, we first introduce the MADES language, which enables rapid system design and specification that can be then taken by underlying MADES tools for goals such as simulation or code generation. Finally, we illustrate the various concepts present in the MADES language by means of a car collision avoidance system case study

Specifying timing requirements in domain specific languages for modeling

Complex Real-Time Embedded Systems (RTESs) can be developed using model-based engineering. The problem is choosing a modeling language that has capabilities to model the most important characteristic of RTESs: timing. This paper shows an analysis of the most popular modeling languages and their capabilities to model timing constraints in RTESs. It includes UML, SysML, AADL, MARTE and EAST-ADL. A brief comparison between MARTE and EAST-ADL, based on the case study from the automotive industry, is also included

A model for requirements traceability in an heterogeneous model-based design process. Application to automotive embedded systems

Requirements traceability modeling is a key issue in real-time embedded design process. In such systems, requirements are of different nature (software-related, system-related, functional and non functional) and must be traced through a multi level design flow which integrates multiple and heterogeneous models. Validation and Verification (V&V) activities must be performed on models and on the final product to check if they are matching the initial require-ments. Results of a design and of V&V activities must impact the traceability information. We propose the DARWIN4REQ metamodel for requirement traceability based on three indepen-dent flows (requirement model, solution model and V&V model). The DARWIN4REQ metamodel establishes the link between these flows and allows a full traceability of requirements including the heterogeneous models. This paper presents the DARWIN4REQ metamodel and its use in the context of heterogeneous models for requirement modeling, design and V&V. An automotive application illustrates the approach with SYSML, EAST_ADL2 and MARTE for the design and SIMULINK, SyNDEx and TIMESQUARE for V&V activities

A Framework for Executable Systems Modeling

Systems Modeling Language (SysML), like its parent language, the Unified Modeling Language (UML), consists of a number of independently derived model languages (i.e. state charts, activity models etc.) which have been co-opted into a single modeling framework. This, together with the lack of an overarching meta-model that supports uniform semantics across the various diagram types, has resulted in a large unwieldy and informal language schema. Additionally, SysML does not offer a built in framework for managing time and the scheduling of time based events in a simulation. In response to these challenges, a number of auxiliary standards have been offered by the Object Management Group (OMG); most pertinent here are the foundational UML subset (fUML), Action language for fUML (Alf), and the UML profile for Modeling and Analysis of Real Time and Embedded Systems (MARTE). However, there remains a lack of a similar treatment of SysML tailored towards precise and formal modeling in the systems engineering domain. This work addresses this gap by offering refined semantics for SysML akin to fUML and MARTE standards, aimed at primarily supporting the development of time based simulation models typically applied for model verification and validation in systems engineering. The result of this work offers an Executable Systems Modeling Language (ESysML) and a prototype modeling tool that serves as an implementation test bed for the ESysML language. Additionally a model development process is offered to guide user appropriation of the provided framework for model building

Supporting ISO 26262 with SysML, Benefits and Limits

International audienceThis article deals with the issue of deploying efficiently the ISO 26262: the new standard in automotive systems development. The directives enclosed in this norm demands the establishment of a product lifecycle fully integrating the safety assessment activities. To tackle this subject, this paper explores the way of setting up Model-Based Design methodology to express and organize the concepts manipulated during the ISO 26262 process. This attempt is founded on the use of SysML and on the creation of a profile dedicated to ISO 26262 development context. We provide an introduction to Model-Based Design paradigm and its appli-cation in a safety relevant context. An overview of ISO 26262 is given, followed by the description of an on-going project on the subject. Modeling propositions are formulated and the use of diverse SysML diagrams are mapped on the automotive safety lifecycle process

Multi-View Power Modeling based on UML MARTE and SysML

The development of SoC involves different activities, usually driven by specialists. These specialists use specific languages and tools to manipulate their specific concepts. The problem is that the multiple views of the system are split into different tools with redundant information. It makes it difficult to ensure consistency as well as to change from one tool to another. We propose a multi-view model where each view represents the specialist concepts in a tool-agnostic manner. The model can be kept consistent by using explicit associations instead of redundancy and tool transformation can be performed to analysis-specific tools. The approach is based on UML and two of its extensions: MARTE and SysML. It is illustrated by adding specific views to specify power management techniques. The resulting model is then transformed into a tool-specific model; \ie a model for Docea Aceplorer, a power analysis tool

Expressing Measurement Uncertainty in OCL/UML Datatypes

Uncertainty is an inherent property of any measure or estimation performed in any physical setting, and therefore it needs to be considered when modeling systems that manage real data. Although several modeling languages permit the representation of measurement uncertainty for describing certain system attributes, these aspects are not normally incorporated into their type systems. Thus, operating with uncertain values and propagating uncertainty are normally cumbersome processes, di cult to achieve at the model level. This paper proposes an extension of OCL and UML datatypes to incorporate data uncertainty coming from physical measurements or user estimations into the models, along with the set of operations de ned for the values of these types.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Analysis as first-class citizens – an application to Architecture Description Languages

Architecture Description Languages (ADLs) support modeling and analysis of systems through models transformation and exploration. Various contributions made proposals to bring verification capabilities to designers through model-based frame- works and illustrated benefits to the overall system quality. Model-level analyses are usually performed as an exogenous, unidirectional and semantically weak transformation towards a third-party model. We claim such process can be incomplete and/or inefficient because gathered results lead to evolution of the primary model. This is particularly problematic for the design of Distributed Real-Time Embedded (DRE) systems that has to tackle many concerns like time, security or safety. In this paper, we argue why analysis should no longer be considered as a side step in the design process but, rather, should be embedded as a first-class citizen in the model itself. We review several standardized architecture description languages, which consider analysis as a goal. As an element of solution, we introduce current work on the definition of a language dedicated to the analysis of models within the scope of one particular ADL, namely the Architecture Analysis and Design Language (AADL)