10,847 research outputs found
Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models
The upcoming many-core architectures require software developers to exploit
concurrency to utilize available computational power. Today's high-level
language virtual machines (VMs), which are a cornerstone of software
development, do not provide sufficient abstraction for concurrency concepts. We
analyze concrete and abstract concurrency models and identify the challenges
they impose for VMs. To provide sufficient concurrency support in VMs, we
propose to integrate concurrency operations into VM instruction sets.
Since there will always be VMs optimized for special purposes, our goal is to
develop a methodology to design instruction sets with concurrency support.
Therefore, we also propose a list of trade-offs that have to be investigated to
advise the design of such instruction sets.
As a first experiment, we implemented one instruction set extension for
shared memory and one for non-shared memory concurrency. From our experimental
results, we derived a list of requirements for a full-grown experimental
environment for further research
Cache Hierarchy Inspired Compression: a Novel Architecture for Data Streams
We present an architecture for data streams based on structures typically found in web cache hierarchies. The main idea is to build a meta level analyser from a number of levels constructed over time from a data stream. We present the general architecture for such a system and an application to classification. This architecture is an instance of the general wrapper idea allowing us to reuse standard batch learning algorithms in an inherently incremental learning environment. By artificially generating data sources we demonstrate that a hierarchy containing a mixture of models is able to adapt over time to the source of the data. In these experiments the hierarchies use an elementary performance based replacement policy and unweighted voting for making classification decisions
STT-RAM์ ์ด์ฉํ ์๋์ง ํจ์จ์ ์ธ ์บ์ ์ค๊ณ ๊ธฐ์
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ)-- ์์ธ๋ํ๊ต ๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ปดํจํฐ๊ณตํ๋ถ, 2019. 2. ์ต๊ธฐ์.์ง๋ ์์ญ ๋
๊ฐ '๋ฉ๋ชจ๋ฆฌ ๋ฒฝ' ๋ฌธ์ ๋ฅผ ํด๊ฒฐํ๊ธฐ ์ํด ์จ ์นฉ ์บ์์ ํฌ๊ธฐ๋ ๊พธ์คํ ์ฆ๊ฐํด์๋ค. ํ์ง๋ง ์ง๊ธ๊น์ง ์บ์์ ์ฃผ๋ก ์ฌ์ฉ๋์ด ์จ ๋ฉ๋ชจ๋ฆฌ ๊ธฐ์ ์ธ SRAM์ ๋ฎ์ ์ง์ ๋์ ๋์ ๋๊ธฐ ์ ๋ ฅ ์๋ชจ๋ก ์ธํด ํฐ ์บ์๋ฅผ ๊ตฌ์ฑํ๋ ๋ฐ์๋ ์ ํฉํ์ง ์๋ค. ์ด๋ฌํ SRAM์ ๋จ์ ์ ๋ณด์ํ๊ธฐ ์ํด ๋ ๋์ ์ง์ ๋์ ๋ฎ์ ๋๊ธฐ ์ ๋ ฅ์ ์๋ชจํ๋ ์๋ก์ด ๋ฉ๋ชจ๋ฆฌ ๊ธฐ์ ์ธ STT-RAM์ผ๋ก SRAM์ ๋์ฒดํ๋ ๊ฒ์ด ์ ์๋์๋ค. ํ์ง๋ง STT-RAM์ ๋ฐ์ดํฐ๋ฅผ ์ธ ๋ ๋ง์ ์๋์ง์ ์๊ฐ์ ์๋นํ๊ธฐ ๋๋ฌธ์ ๋จ์ํ SRAM์ STT-RAM์ผ๋ก ๋์ฒดํ๋ ๊ฒ์ ์คํ๋ ค ์บ์ ์๋์ง ์๋น๋ฅผ ์ฆ๊ฐ์ํจ๋ค. ์ด๋ฌํ ๋ฌธ์ ๋ฅผ ํด๊ฒฐํ๊ธฐ ์ํด ๋ณธ ๋
ผ๋ฌธ์์๋ STT-RAM์ ์ด์ฉํ ์๋์ง ํจ์จ์ ์ธ ์บ์ ์ค๊ณ ๊ธฐ์ ๋ค์ ์ ์ํ๋ค.
์ฒซ ๋ฒ์งธ, ๋ฐฐํ์ ์บ์ ๊ณ์ธต ๊ตฌ์กฐ์์ STT-RAM์ ํ์ฉํ๋ ๋ฐฉ๋ฒ์ ์ ์ํ์๋ค. ๋ฐฐํ์ ์บ์ ๊ณ์ธต ๊ตฌ์กฐ๋ ๊ณ์ธต ๊ฐ์ ์ค๋ณต๋ ๋ฐ์ดํฐ๊ฐ ์๊ธฐ ๋๋ฌธ์ ํฌํจ์ ์บ์ ๊ณ์ธต ๊ตฌ์กฐ์ ๋น๊ตํ์ฌ ๋ ํฐ ์ ํจ ์ฉ๋์ ๊ฐ์ง๋ง, ๋ฐฐํ์ ์บ์ ๊ณ์ธต ๊ตฌ์กฐ์์๋ ์์ ๋ ๋ฒจ ์บ์์์ ๋ด๋ณด๋ด์ง ๋ชจ๋ ๋ฐ์ดํฐ๋ฅผ ํ์ ๋ ๋ฒจ ์บ์์ ์จ์ผ ํ๋ฏ๋ก ๋ ๋ง์ ์์ ๋ฐ์ดํฐ๋ฅผ ์ฐ๊ฒ ๋๋ค. ์ด๋ฌํ ๋ฐฐํ์ ์บ์ ๊ณ์ธต ๊ตฌ์กฐ์ ํน์ฑ์ ์ฐ๊ธฐ ํน์ฑ์ด ๋จ์ ์ธ STT-RAM์ ํจ๊ป ํ์ฉํ๋ ๊ฒ์ ์ด๋ ต๊ฒ ํ๋ค. ์ด๋ฅผ ํด๊ฒฐํ๊ธฐ ์ํด ๋ณธ ๋
ผ๋ฌธ์์๋ ์ฌ์ฌ์ฉ ๊ฑฐ๋ฆฌ ์์ธก์ ๊ธฐ๋ฐ์ผ๋ก ํ๋ SRAM/STT-RAM ํ์ด๋ธ๋ฆฌ๋ ์บ์ ๊ตฌ์กฐ๋ฅผ ์ค๊ณํ์๋ค.
๋ ๋ฒ์งธ, ๋นํ๋ฐ์ฑ STT-RAM์ ์ด์ฉํด ์บ์๋ฅผ ์ค๊ณํ ๋ ๊ณ ๋ คํด์ผ ํ ์ ๋ค์ ๋ํด ๋ถ์ํ์๋ค. STT-RAM์ ๋นํจ์จ์ ์ธ ์ฐ๊ธฐ ๋์์ ์ค์ด๊ธฐ ์ํด ๋ค์ํ ํด๊ฒฐ๋ฒ๋ค์ด ์ ์๋์๋ค. ๊ทธ์ค ํ ๊ฐ์ง๋ STT-RAM ์์๊ฐ ๋ฐ์ดํฐ๋ฅผ ์ ์งํ๋ ์๊ฐ์ ์ค์ฌ (ํ๋ฐ์ฑ STT-RAM) ์ฐ๊ธฐ ํน์ฑ์ ํฅ์ํ๋ ๋ฐฉ๋ฒ์ด๋ค. STT-RAM์ ์ ์ฅ๋ ๋ฐ์ดํฐ๋ฅผ ์๋ ๊ฒ์ ํ๋ฅ ์ ์ผ๋ก ๋ฐ์ํ๊ธฐ ๋๋ฌธ์ ์ ์ฅ๋ ๋ฐ์ดํฐ๋ฅผ ์์ ์ ์ผ๋ก ์ ์งํ๊ธฐ ์ํด์๋ ์ค๋ฅ ์ ์ ๋ถํธ(ECC)๋ฅผ ์ด์ฉํด ์ฃผ๊ธฐ์ ์ผ๋ก ์ค๋ฅ๋ฅผ ์ ์ ํด์ฃผ์ด์ผ ํ๋ค. ๋ณธ ๋
ผ๋ฌธ์์๋ STT-RAM ๋ชจ๋ธ์ ์ด์ฉํ์ฌ ํ๋ฐ์ฑ STT-RAM ์ค๊ณ ์์๋ค์ ๋ํด ๋ถ์ํ์๊ณ ์คํ์ ํตํด ํด๋น ์ค๊ณ ์์๋ค์ด ์บ์ ์๋์ง์ ์ฑ๋ฅ์ ์ฃผ๋ ์ํฅ์ ๋ณด์ฌ์ฃผ์๋ค.
๋ง์ง๋ง์ผ๋ก, ๋งค๋์ฝ์ด ์์คํ
์์์ ๋ถ์ฐ ํ์ด๋ธ๋ฆฌ๋ ์บ์ ๊ตฌ์กฐ๋ฅผ ์ค๊ณํ์๋ค. ๋จ์ํ ๊ธฐ์กด์ ํ์ด๋ธ๋ฆฌ๋ ์บ์์ ๋ถ์ฐ์บ์๋ฅผ ๊ฒฐํฉํ๋ฉด ํ์ด๋ธ๋ฆฌ๋ ์บ์์ ํจ์จ์ฑ์ ํฐ ์ํฅ์ ์ฃผ๋ SRAM ํ์ฉ๋๊ฐ ๋ฎ์์ง๋ค. ๋ฐ๋ผ์ ๊ธฐ์กด์ ํ์ด๋ธ๋ฆฌ๋ ์บ์ ๊ตฌ์กฐ์์์ ์๋์ง ๊ฐ์๋ฅผ ๊ธฐ๋ํ ์ ์๋ค. ๋ณธ ๋
ผ๋ฌธ์์๋ ๋ถ์ฐ ํ์ด๋ธ๋ฆฌ๋ ์บ์ ๊ตฌ์กฐ์์ SRAM ํ์ฉ๋๋ฅผ ๋์ผ ์ ์๋ ๋ ๊ฐ์ง ์ต์ ํ ๊ธฐ์ ์ธ ๋ฑ
ํฌ-๋ด๋ถ ์ต์ ํ์ ๋ฑ
ํฌ๊ฐ ์ต์ ํ ๊ธฐ์ ์ ์ ์ํ์๋ค. ๋ฑ
ํฌ-๋ด๋ถ ์ต์ ํ๋ highly-associative ์บ์๋ฅผ ํ์ฉํ์ฌ ๋ฑ
ํฌ ๋ด๋ถ์์ ์ฐ๊ธฐ ๋์์ด ๋ง์ ๋ฐ์ดํฐ๋ฅผ ๋ถ์ฐ์ํค๋ ๊ฒ์ด๊ณ ๋ฑ
ํฌ๊ฐ ์ต์ ํ๋ ์๋ก ๋ค๋ฅธ ์บ์ ๋ฑ
ํฌ์ ์ฐ๊ธฐ ๋์์ด ๋ง์ ๋ฐ์ดํฐ๋ฅผ ๊ณ ๋ฅด๊ฒ ๋ถ์ฐ์ํค๋ ์ต์ ํ ๋ฐฉ๋ฒ์ด๋ค.Over the last decade, the capacity of on-chip cache is continuously increased to mitigate the memory wall problem. However, SRAM, which is a dominant memory technology for caches, is not suitable for such a large cache because of its low density and large static power. One way to mitigate these downsides of the SRAM cache is replacing SRAM with a more efficient memory technology. Spin-Transfer Torque RAM (STT-RAM), one of the emerging memory technology, is a promising candidate for the alternative of SRAM. As a substitute of SRAM, STT-RAM can compensate drawbacks of SRAM with its non-volatility and small cell size. However, STT-RAM has poor write characteristics such as high write energy and long write latency and thus simply replacing SRAM to STT-RAM increases cache energy. To overcome those poor write characteristics of STT-RAM, this dissertation explores three different design techniques for energy-efficient cache using STT-RAM.
The first part of the dissertation focuses on combining STT-RAM with exclusive cache hierarchy. Exclusive caches are known to provide higher effective cache capacity than inclusive caches by removing duplicated copies of cache blocks across hierarchies. However, in exclusive cache hierarchies, every block evicted from the upper-level cache is written back to the last-level cache regardless of its dirtiness thereby incurring extra write overhead. This makes it challenging to use STT-RAM for exclusive last-level caches due to its high write energy and long write latency. To mitigate this problem, we design an SRAM/STT-RAM hybrid cache architecture based on reuse distance prediction.
The second part of the dissertation explores trade-offs in the design of volatile STT-RAM cache. Due to the inefficient write operation of STT-RAM, various solutions have been proposed to tackle this inefficiency. One of the proposed solutions is redesigning STT-RAM cell for better write characteristics at the cost of shortened retention time (i.e., volatile STT-RAM). Since the retention failure of STT-RAM has a stochastic property, an extra overhead of periodic scrubbing with error correcting code (ECC) is required to tolerate the failure. With an analysis based on analytic STT-RAM model, we have conducted extensive experiments on various volatile STT-RAM cache design parameters including scrubbing period, ECC strength, and target failure rate. The experimental results show the impact of the parameter variations on last-level cache energy and performance and provide a guideline for designing a volatile STT-RAM with ECC and scrubbing.
The last part of the dissertation proposes Benzene, an energy-efficient distributed SRAM/STT-RAM hybrid cache architecture for manycore systems running multiple applications. It is based on the observation that a naive application of hybrid cache techniques to distributed caches in a manycore architecture suffers from limited energy reduction due to uneven utilization of scarce SRAM. We propose two-level optimization techniques: intra-bank and inter-bank. Intra-bank optimization leverages highly-associative cache design, achieving more uniform distribution of writes within a bank. Inter-bank optimization evenly balances the amount of write-intensive data across the banks.Abstract i
Contents iii
List of Figures vii
List of Tables xi
Chapter 1 Introduction 1
1.1 Exclusive Last-Level Hybrid Cache 2
1.2 Designing Volatile STT-RAM Cache 4
1.3 Distributed Hybrid Cache 5
Chapter 2 Background 9
2.1 STT-RAM 9
2.1.1 Thermal Stability 10
2.1.2 Read and Write Operation of STT-RAM 11
2.1.3 Failures of STT-RAM 11
2.1.4 Volatile STT-RAM 13
2.1.5 Related Work 14
2.2 Exclusive Last-Level Hybrid Cache 18
2.2.1 Cache Hierarchies 18
2.2.2 Related Work 19
2.3 Distributed Hybrid Cache 21
2.3.1 Prediction Hybrid Cache 21
2.3.2 Distributed Cache Partitioning 22
2.3.3 Related Work 23
Chapter 3 Exclusive Last-Level Hybrid Cache 27
3.1 Motivation 27
3.1.1 Exclusive Cache Hierarchy 27
3.1.2 Reuse Distance 29
3.2 Architecture 30
3.2.1 Reuse Distance Predictor 30
3.2.2 Hybrid Cache Architecture 32
3.3 Evaluation 34
3.3.1 Methodology 34
3.3.2 LLC Energy Consumption 35
3.3.3 Main Memory Energy Consumption 38
3.3.4 Performance 39
3.3.5 Area Overhead 39
3.4 Summary 39
Chapter 4 Designing Volatile STT-RAM Cache 41
4.1 Analysis 41
4.1.1 Retention Failure of a Volatile STT-RAM Cell 41
4.1.2 Memory Array Design 43
4.2 Evaluation 45
4.2.1 Methodology 45
4.2.2 Last-Level Cache Energy 46
4.2.3 Performance 51
4.3 Summary 52
Chapter 5 Distributed Hybrid Cache 55
5.1 Motivation 55
5.2 Architecture 58
5.2.1 Intra-Bank Optimization 59
5.2.2 Inter-Bank Optimization 63
5.2.3 Other Optimizations 67
5.3 Evaluation Methodology 69
5.4 Evaluation Results 73
5.4.1 Energy Consumption and Performance 73
5.4.2 Analysis of Intra-bank Optimization 76
5.4.3 Analysis of Inter-bank Optimization 78
5.4.4 Impact of Inter-Bank Optimization on Network Energy 79
5.4.5 Sensitivity Analysis 80
5.4.6 Implementation Overhead 81
5.5 Summary 82
Chapter 6 Conculsion 85
Bibliography 88
์ด๋ก 101Docto
Energy Saving Techniques for Phase Change Memory (PCM)
In recent years, the energy consumption of computing systems has increased
and a large fraction of this energy is consumed in main memory. Towards this,
researchers have proposed use of non-volatile memory, such as phase change
memory (PCM), which has low read latency and power; and nearly zero leakage
power. However, the write latency and power of PCM are very high and this,
along with limited write endurance of PCM present significant challenges in
enabling wide-spread adoption of PCM. To address this, several
architecture-level techniques have been proposed. In this report, we review
several techniques to manage power consumption of PCM. We also classify these
techniques based on their characteristics to provide insights into them. The
aim of this work is encourage researchers to propose even better techniques for
improving energy efficiency of PCM based main memory.Comment: Survey, phase change RAM (PCRAM
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