Automatic Derivation of Abstract Semantics From Instruction Set Descriptions

Abstracted semantics of instructions of processor-based architectures are an invaluable asset for several formal verification techniques, such as software model checking and static analysis. In the field of model checking, abstract versions of instructions can help counter the state explosion problem, for instance by replacing explicit values by symbolic representations of sets of values. Similar to this, static analyses often operate on an abstract domain in order to reduce complexity, guarantee termination, or both. Hence, for a given microcontroller, the task at hand is to find such abstractions. Due to the large number of available microcontrollers, some of which are even created for specific applications, it is impracticable to rely on human developers to perform this step. Therefore, we propose a technique that starts from imperative descriptions of instructions, which allows to automate most of the process

Bridging the Gap between Enumerative and Symbolic Model Checkers

We present a method to perform symbolic state space generation for languages with existing enumerative state generators. The method is largely independent from the chosen modelling language. We validated this on three different types of languages and tools: state-based languages (PROMELA), action-based process algebras (muCRL, mCRL2), and discrete abstractions of ODEs (Maple).\ud Only little information about the combinatorial structure of the\ud underlying model checking problem need to be provided. The key enabling data structure is the "PINS" dependency matrix. Moreover, it can be provided gradually (more precise information yield better results).\ud \ud Second, in addition to symbolic reachability, the same PINS matrix contains enough information to enable new optimizations in state space generation (transition caching), again independent from the chosen modelling language. We have also based existing optimizations, like (recursive) state collapsing, on top of PINS and hint at how to support partial order reduction techniques.\ud \ud Third, PINS allows interfacing of existing state generators to, e.g., distributed reachability tools. Thus, besides the stated novelties, the method we propose also significantly reduces the complexity of building modular yet still efficient model checking tools.\ud \ud Our experiments show that we can match or even outperform existing tools by reusing their own state generators, which we have linked into an implementation of our ideas

Random Modulo: A new processor cache design for real-time critical systems

Cache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, caches complicate timing analysis. In the context of Measurement-Based Probabilistic Timing Analysis (MBPTA) - a promising technique to ease timing analyis of complex hardware - we propose Random Modulo (RM), a new cache design that provides the probabilistic behavior required by MBPTA and with the following advantages over existing MBPTA-compliant cache designs: (i) an outstanding reduction in WCET estimates, (ii) lower latency and area overhead, and (iii) competitive average performance w.r.t conventional caches.Peer ReviewedPostprint (author's final draft

Efficient Memory-Protected Integration of Add-On Software Subsystems in Small Embedded Automotive Applications

Current innovations in the automotive industry evolve mainly in the electronics and software domain. This leads to an increasing integration of additional software subsystems into already existing electronic control units (ECUs) to cope with the raised amount and complexity of present ECUs in modern high-end vehicles. This paper discusses different approaches which are required to integrate such add-on software subsystems in an isolated memory domain, and considers particularly the special needs of small embedded systems—including the limited hardware support. Special focus is brought to the efficient detection of malicious memory accesses, as well as the benefits of a thereupon possible and adaptable failure-handling strategy. All investigations are based on a developed memory-protection framework which has been tailored to the special needs of a sample vehicle dynamics control system. Its usage allows the combination of. integrating additional subsystems without reducing the main application’s availability

The Real Time Hardware Design and simulation of moving message Display System Integrated with PLCC Modem

This paper serves as a general and technical orientation on the one of application of  "Power line Carrier (PLC) Communication Systems" with scrolling message on LED/LCD with keyboard facility in real time with the presentation of a widespread and detailed analysis on the standards, characteristics, technologies, products and development associated and currently being deployed in the PLC communication systems. Since the developments and research on the subject had been relatively new in India and information scattered, the lack of collective information had been the primary Initiative behind this research. Power Line Carrier (PLC) is still widely used to provide real-time communications for protection of high voltage transmission lines. This PLCC module provides bi-directional half-duplex communication over the mains of any voltage up to (220-250)V AC and for frequency 50 Hz or 60 Hz. Usually modules is in receiving mode all the time attending to incoming communication on the power line. This application gives serial data to transmit on its RX-IN pin, it switches over to transmit and transmits the data through power line. Once transmit process is complete it switches back to receive mode. During transmission of data by Red LED indicates user that data is transmitting. At the receiving end receipt data  indicated by Green LED which is on TX out pin itself. Data communication of the modules is clear to user’s data terminals and protocol self-determining; as a result, multiple units can be connected to the mains without affecting the operation of the others. In this we can connect the PLC modem to the Atmega 16 controller and then program it and simulated with ISP connector and then at last connect PLC system to the AC power plug.   Keywords :  PLCC Modem ,LED Panels, Keyboard decode

Proceedings of the 4th field robot event 2006, Stuttgart/Hohenheim, Germany, 23-24th June 2006

Zeer uitgebreid verslag van het 4e Fieldrobotevent, dat gehouden werd op 23 en 24 juni 2006 in Stuttgart/Hohenhei

Intelligent Systems Development in a Non Engineering Curriculum

Much of computer system development today is programming in the large - systems of millions of lines of code distributed across servers and the web. At the same time, microcontrollers have also become pervasive in everyday products, economical to manufacture, and represent a different level of learning about system development. Real world systems at this level require integrated development of custom hardware and software. How can academic institutions give students a view of this other extreme - programming on small microcontrollers with specialized hardware? Full scale system development including custom hardware and software is expensive, beyond the range of any but the larger engineering oriented universities, and hard to fit into a typical length course. The course described here is a solution using microcontroller programming in high level language, small hardware components, and the Arduino open source microcontroller. The results of the hands-on course show that student programmers with limited hardware knowledge are able to build custom devices, handle the complexity of basic hardware design, and learn to appreciate the differences between large and small scale programming