29,726 research outputs found
A Reuse-based framework for the design of analog and mixed-signal ICs
Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.Ministerio de Educación y Ciencia TEC2004-0175
From FPGA to ASIC: A RISC-V processor experience
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC
MISSED: an environment for mixed-signal microsystem testing and diagnosis
A tight link between design and test data is proposed for speeding up test-pattern generation and diagnosis during mixed-signal prototype verification. Test requirements are already incorporated at the behavioral level and specified with increased detail at lower hierarchical levels. A strict distinction between generic routines and implementation data makes reuse of software possible. A testability-analysis tool and test and DFT libraries support the designer to guarantee testability. Hierarchical backtrace procedures in combination with an expert system and fault libraries assist the designer during mixed-signal chip debuggin
On the Verification of a WiMax Design Using Symbolic Simulation
In top-down multi-level design methodologies, design descriptions at higher
levels of abstraction are incrementally refined to the final realizations.
Simulation based techniques have traditionally been used to verify that such
model refinements do not change the design functionality. Unfortunately, with
computer simulations it is not possible to completely check that a design
transformation is correct in a reasonable amount of time, as the number of test
patterns required to do so increase exponentially with the number of system
state variables. In this paper, we propose a methodology for the verification
of conformance of models generated at higher levels of abstraction in the
design process to the design specifications. We model the system behavior using
sequence of recurrence equations. We then use symbolic simulation together with
equivalence checking and property checking techniques for design verification.
Using our proposed method, we have verified the equivalence of three WiMax
system models at different levels of design abstraction, and the correctness of
various system properties on those models. Our symbolic modeling and
verification experiments show that the proposed verification methodology
provides performance advantage over its numerical counterpart.Comment: In Proceedings SCSS 2012, arXiv:1307.802
A system-on-chip digital pH meter for use in a wireless diagnostic capsule
This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units
The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips
The foreseen Phase 2 pixel upgrades at the LHC have very challenging
requirements for the design of hybrid pixel readout chips. A versatile pixel
simulation platform is as an essential development tool for the design,
verification and optimization of both the system architecture and the pixel
chip building blocks (Intellectual Properties, IPs). This work is focused on
the implemented simulation and verification environment named VEPIX53, built
using the SystemVerilog language and the Universal Verification Methodology
(UVM) class library in the framework of the RD53 Collaboration. The environment
supports pixel chips at different levels of description: its reusable
components feature the generation of different classes of parameterized input
hits to the pixel matrix, monitoring of pixel chip inputs and outputs,
conformity checks between predicted and actual outputs and collection of
statistics on system performance. The environment has been tested performing a
study of shared architectures of the trigger latency buffering section of pixel
chips. A fully shared architecture and a distributed one have been described at
behavioral level and simulated; the resulting memory occupancy statistics and
hit loss rates have subsequently been compared.Comment: 15 pages, 10 figures (11 figure files), submitted to Journal of
Instrumentatio
The multiple-function multi-input/multi-output digital controller system for the AFW wind-tunnel model
A real time multiple-function digital controller system was developed for the Active Flexible Wing (AFW) Program. The digital controller system (DCS) allowed simultaneous execution of two control laws: flutter suppression and either roll trim or a rolling maneuver load control. The DCS operated within, but independently of, a slower host operating system environment, at regulated speeds up to 200 Hz. It also coordinated the acquisition, storage, and transfer of data for near real time controller performance evaluation and both open- and closed-loop plant estimation. It synchronized the operation of four different processing units, allowing flexibility in the number, form, functionality, and order of control laws, and variability in the selection of the sensors and actuators employed. Most importantly, the DCS allowed for the successful demonstration of active flutter suppression to conditions approximately 26 percent (in dynamic pressure) above the open-loop boundary in cases when the model was fixed in roll and up to 23 percent when it was free to roll. Aggressive roll maneuvers with load control were achieved above the flutter boundary. The purpose here is to present the development, validation, and wind tunnel testing of this multiple-function digital controller system
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