1,027 research outputs found
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE
A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally
A 2.4 Ghz Mimo Wireless Transceiver Design [TK5103.2. Q1 2008 f rb].
Kombinasi antara MIMO dan modulasi kesukuan dianggap sebagai salah satu penyelesaian yang paling berkesan bagi memperbaiki kecekapan spektrum dan meningkatkan kadar data untuk sistem komonikasi tanpa wayar bagi generasi akan datang .
The combination of multiple input multiple output (MIMO) and quadrature modulation is regarded as one of the most promising solutions for improving spectrum efficiency and enhancing data rate for next-generation wireless communication systems
Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications
As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well
Design of adaptive analog filters for magnetic front-end read channels
Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de
muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem
para canais de leitura em sistemas de gravação e reprodução de dados em suporte
magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a
1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste
trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços
muito significativos a nível mundial com o objectivo de se investigarem novas técnicas
de realização de filtros em circuito integrado monolítico, especialmente em tecnologia
CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo
a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização
de soluções com as características desejadas.
Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão
de sinal bem como a escolha de bons modelos matemáticos para o tratamento da
informação e a minimização de erro inerente às aproximações na conformidade aos princípios
físicos dos dispositivos caracterizados.
O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do
canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de
filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado
sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte
magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo,
baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia
digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization)
com base na igualização de sinal utilizando filtros integrados analógicos em tempo
contínuo.
Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação
de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que
a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros
adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo,
dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa
e análise de estruturas ideais no projecto de filtros recorrendo a representações no
espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de
circuitos de transcondutância para a implementação de filtros integrados analógicos em
tempo contínuo.
Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros
no espaço de estados, correspondentes a duas soluções alternativas para a realização de
um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem,
para utilização num canal de leitura de dados em suporte magnético.
Como parte constituinte destes filtros, apresenta-se uma técnica de realização de
circuitos de transcondutância, e de realização de condensadores lineares usando matrizes
de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada
em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se
métodos de adaptação automática capazes de compensar os erros face aos valores nominais
dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os
quais apresentamos os resultados de simulação e de medição experimental obtidos.
Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível
de constituir uma solução para o controlo de posicionamento da cabeça de leitura
em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto
é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância
e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo
de igualação do canal de leitura.
Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de
controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em
Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa
utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency
filters. The motivation of this work was the search for filtering solutions for the readchannel
in recording and reproduction of data on magnetic media systems, with costs and
consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than
the available circuits. Accordingly, as was done in this work, the rapid development of
microelectronics technology raised very significant efforts worldwide in order to investigate
new techniques for implementing such filters in monolithic integrated circuit, especially
in CMOS technology (Complementary Metal Oxide Semiconductor). We present
a comparative study on different hierarchical levels of the project, which led to the realization
and characterization of solutions with the desired characteristics.
In the first level, this study addresses the conceptual question of recording and
transmission of signal and the choice of good mathematical models for the processing of
information and minimization of error inherent in the approaches and in accordance with
the principles of the characterized physical devices.
The main work of this thesis is focused on the hierarchical levels of the architecture
of the read channel and the integrated circuit implementation of its main block - the filtering
block. At the architecture level of the read channel this work presents a comprehensive
study on existing methodologies of adaptation and signal recovery of data on
magnetic media. This project appears in the sequence of the proposed solution for a lowcost,
low consumption, low voltage, low complexity, using CMOS digital technology for
the performance of a DFE (Decision Feedback Equalization) based on the equalization of
the signal using integrated analog filters in continuous time.
At the project level of implementation of the filtering block and techniques for implementing
filters and its building components, it was concluded that the technique based
on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate
for the implementation of very-high-frequency adaptive filters. We defined in
this lower level, two sub-levels of depth study for this thesis, namely: research and analysis
of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation
of continuous time integrated analog filters.
Following this study, we present and compare two filtering structures operating in
the space of states, corresponding to two alternatives for achieving a realization of an
adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a
read-channel for magnetic media devices.
As a constituent part of these filters, we present a technique for the realization of
transconductance circuits and for the implementation of linear capacitors using arrays of
MOSFET transistors for signal processing in very-high-frequency integrated circuits using
sub-micrometric CMOS technology. We present methods capable of automatic adjustment
and compensation for deviation errors in respect to the nominal values of the
components inherent to the tolerances of the fabrication process, for which we present
the simulation and experimental measurement results obtained.
Also as a result of this study, is the presentation of a circuit that provides a solution
for the control of the head positioning on recording/playback systems of data on magnetic
media. The proposed block is an adaptive first-order filter, based on the same transconductance
circuits and equalization techniques proposed and used in the implementation
of the adaptive filter for the equalization of the read channel.
This filter was designed and included in an integrated circuit (Jaguar) used to control
the positioning of the read-head done for ATMEL company in Colorado Springs, and
part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company
A fully integrated 24-GHz phased-array transmitter in CMOS
This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area
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Silicon Photonic Subsystems for Inter-Chip Optical Networks
The continuous growth of electronic compute and memory nodes in terms of the number of I/O pins, bandwidth, and areal throughput poses major integration and packaging challenges associated with offloading multi-Tbit/s data rates within the few pJ/bit targets. While integrated photonics are already deployed in long and short distances such as inter and intra data centers communications, the promising characteristics of the silicon photonic platform set it as the future technology for optical interconnects in ultra short inter-chip distances. The high index contrast between the waveguide and the cladding together with strong thermo-optic and carrier effects in silicon allows developing a wide range of micro-scale and low power optical devices compatible with the CMOS fabrication processes. Furthermore, the availability of photonic foundries and new electrical and optical co-packaging techniques further pushes this platform for the next steps of commercial deployment.
The work in this dissertation presents the current trends in high-performance memory and processor nodes and gives motivation for disaggregated and reconfigurable inter-chip network enabled with the silicon photonic layer. A dense WDM transceiver and broadband switch architectures are discussed to support a bi-directional network of ten hybrid-memory cubes (HMC) interconnected to ten processor nodes with an overall aggregated bandwidth of 9.6Tbit/s. Latency and energy consumption are key performance parameters in a processor to primary memory nodes connectivity. The transceiver design is based on energy-efficient micro-ring resonators, and the broadband switch is constructed with 2x2 Mach-Zehnder elements for nano-second reconfiguration. Each transceiver is based on hundreds of micro-rings to convert the native HMC electrical protocol to the optical domain and the switch is based on tens of hundreds of 2x2 elements to achieve non-blocking all-to-all connectivity.
The next chapters focus on developing methods for controlling and monitoring such complex and highly integrated silicon photonic subsystems. The thermo-optic effect is characterized and we show experimentally that the phase of the optical carrier can be reliably controlled with pulse-width modulation (PWM) signal, ultimately relaxing the need for hundreds of digital to analog converters (DACs). We further show that doped waveguide heaters can be utilized as \textit{in-line} optical power monitors by measuring photo-conductance current, which is an alternative for the conventional tapping and integration of photo-diodes.
The next part concerned with a common cascaded micro-ring resonator in a WDM transceiver design. We develop on an FPGA control algorithm that abstracts the physical layer and takes user-defined inputs to set the resonances to the desired wavelength in a unicast and multicast transmission modes. The associated sensitivities of these silicon ring resonators are presented and addressed with three closed-loop solutions. We first show a closed-loop operation based on tapping the error signal from the drop port of the micro-ring. The second solution presents a resonance wavelength locking with a single digital I/O for control and feedback signals. Lastly, we leverage the photo-conductance effect and demonstrate the locking procedure using only the doped heater for both control and feedback purposes.
To achieve the inter-chip reconfigurability we discuss recent advances of high-port-count SiP broadband switches for reconfigurable inter-chip networks. To ensure optimal operation in terms of low insertion loss, low cross-talk and high signal integrity per routing path, hundreds of 2x2 Mach-Zehnder elements need to be biased precisely for the cross and bar states. We address this challenge with a tapless and a design agnostic calibration approach based on the photo-conductance effect. The automated algorithm returns a look-up table for all for each 2x2 element and the associated calibrated biases. Each routing scenario is then tested for insertion loss, crosstalk and bit-error rate of 25Gbit/s 4-level pulse amplitude modulation signals. The last part utilizes the Mach-Zehnder interferometers in WDM transceiver applications. We demonstrate a polarization insensitive four-channel WDM receiver with 40Gbit/s per channel and a transmitter design generating 8-level pulse amplitude modulation signals at 30Gbit/s
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