System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Circuit design and technological limitations of silicon RFICs for wireless applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 201-206).Semiconductor technologies have been a key to the growth in wireless communication over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power dissipation. A better understanding of how an IC technology affects critical RF signal chain components will greatly aid the design of wireless systems and the development of process technologies for the increasingly complex applications that lie on the horizon. Many of the evolving applications will embody the concept of adaptive performance to extract the maximum capability from the RF link in terms of bandwidth, dynamic range, and power consumption-further engaging the interplay of circuits and devices is this design space and making it even more difficult to discern a clear guide upon which to base technology decisions. Rooted in these observations, this research focuses on two key themes: 1) devising methods of implementing RF circuits which allow the performance to be dynamically tuned to match real-time conditions in a power-efficient manner, and 2) refining approaches for thinking about the optimization of RF circuits at the device level. Working toward a 5.8 GHz receiver consistent with 1 GBit/s operation, signal path topologies and adjustable biasing circuits are developed for low-noise amplifiers (LNAs) and voltage-controlled oscillators (VCOs) to provide a facility by which power can be conserved when the demand for sensitivity is low. As an integral component in this effort, tools for exploring device level issues are illustrated with both circuit types, helping to identify physical limitations and design techniques through which they can be mitigated.(cont.) The design of two LNAs and four VCOs is described, each realized to provide a fully-integrated solution in a 0.5 tm SiGe BiCMOS process, and each incorporating all biasing and impedance matching on chip. Measured results for these 5-6GHz circuits allow a number of poignant technology issues to be enlightened, including an exhibition of the importance of terminal resistances and capacitances, a demonstration of where the transistor fT is relevant and where it is not, and the most direct comparison of bipolar and CMOS solutions offered to date in this frequency range. In addition to covering a number of new circuit techniques, this work concludes with some new views regarding IC technologies for RF applications.by Donald A. Hitko.Ph.D

MILLIMETER-WAVE QUADRATURE RECEIVERS FOR ATMOSPHERIC SENSING AND RADIOMETRY

The objective of this research is to investigate the design challenges of millimeter wave (mm-wave) quadrature receivers for emerging applications and develop new ideas to ad- dress these challenges. Next-generation wireless networks, satellite communications, atmospheric sensing instruments, autonomous vehicle radars, and body scanners are targeting to operate at mm-wave frequencies, and high-performance electronics are needed to enable these technologies. In this research, we investigate novel circuit topologies to improve the performance of existing mm-wave quadrature receivers, particularly for radiometry and remote sensing applications. A transformer-based front-end switch is co- designed with an LNA where the transformer acts as the input matching network of the LNA, reducing the front-end loss and system noise figure. Broadband and low-loss quadrature signal generation networks are proposed to provide highly balanced quadrature signals to reject the image frequency content. In addition, a high-efficiency frequency multiplier topology is demonstrated, achieving superior performance compared to the state-of-the-art designs. Lastly, the reliability and noise performance of on-chip noise source devices (PN junctions) in a SiGe BiCMOS platform was characterized and compared. To confirm the advantages of our ideas, the measurement and simulation results of all fabricated circuits are presented and discussed.Ph.D

Integration of broadband direct-conversion quadrature modulators

To increase spectral efficiency, transmitters usually send only one of the information carrying sidebands centered around a single radio-frequency carrier. The close-lying mirror, or image, sideband will be eliminated either by the filtering method or by the phasing method. Since filter Q-values rise in direct relation to the transmitted frequencies, the filtering method is generally not feasible for integrated microwave transmitters. A quadrature modulator realizes the phasing method by combining signals phased at quadrature (i.e. at 90° offsets) to produce a single-sideband (SSB) output. In this way output filtering can be removed or its specifications greatly relieved so as to produce an economical microwave transmitter. The proliferation of integrated circuit (IC) technologies since the 1980s has further boosted the popularity of quadrature modulator as an IC realization makes possible the economical production of two closely matched doubly balanced mixers, which suppress carrier and even-order spurious leakage to circuit output. Another strength of IC is its ability to perform microwave quadrature generation accurately on-chip, and thereby to avoid most of the interconnect parasitics which could ruin high-frequency quadrature signaling. Nevertheless, all quadrature modulator implementations are sensitive to phasing and amplitude errors, which are born as a result of mismatches, from the use of inaccurate differential signaling, and from inadequacies in the phasing circuitry itself. A 2° phase error is easily produced, and it reduces the image-rejection ratio (IRR) to −30 dBc. Therefore, as baseband signals synthesized by digital signal processing (DSP) are sufficiently accurate, this thesis concentrates on analyzing and producing the microwave signal path of a direct-conversion quadrature modulator with special emphasis on broadband, multimode radio-compatible operation. A model of the direct-conversion quadrature modulator operation has been developed, which reveals the effect the circuit non-linearities and mismatch-related offsets have on available performance. Further, theoretical proof is given of the well-known property of improving differential signal balance that cascaded differential pairs exhibit. Among the practical results, a current reuse mixer has been developed, which improves the transmitted signal-to-noise-ratio (SNR) by 3 dB, with a maximum measured dynamic range of +158 dB. The complementary bipolar process was further used to extend the bipolar push-pull stage bandwidth to 9.5 GHz. At the core of this work is the parallel switchable polyphase (PP) filter quadrature generator that was developed, since it makes possible accurate broadband IQ generation without the high loss that usually results from the application of PP filtering. Two IQ modulator prototypes were realized to test simulated and theoretically derived data: the 0.8 µm SiGe IC achieves an IRR better than −40 dBc over 0.75-3.6 GHz, while the 0.13 µm digital bulk CMOS IC achieves better than −37 dBc over 0.56-4.76 GHz. For this IRR performance the SiGe prototype boasts the inexpensive solution of integrated baluns, while the CMOS one utilizes a coil-transmission line hybrid transformer at its LO input to drive the switchable PP filters.Taajuuksien käytön tehostamiseksi lähettimet lähettävät yleensä vain toisen informaatiota sisältävistä sivukaistoistaan yhdelle radiotaajuuksiselle kantoaallolle keskitettynä. Viereinen peilitaajuus eli sivukaista vaimennetaan joko suodattamalla tai vaiheistamalla signalointia sopivasti. Koska suodattimen hyvyysluvut nousevat suorassa suhteessa käytettyyn taajuuteen, ei suodatusmenetelmä ole yleensä mahdollinen mikroaaltotaajuusalueen lähettimissä. Kvadratuurimodulaattori toteuttaa vaiheistusmenetelmän yhdistämällä 90-asteen vaihesiirroksin vaiheistetut signaalit yksisivukaistaisen lähetteen tuottamiseksi. Näin voidaan korvata lähdön suodatus joko kokonaan tai lieventämällä vaadittavia suoritusarvoja, jolloin mikroaaltoalueen lähetin voidaan tuottaa taloudellisesti. Integroitujen piiriratkaisujen yleistyminen 1980-luvulta lähtien on edesauttanut kvadratuurimodulaattorin suosiota, koska integroidulle piirille voidaan taloudellisesti tuottaa kaksi hyvin ominaisuuksiltaan toisiaan vastaavaa kaksoisbalansoitua sekoitinta, ja nämä tunnetusti vaimentavat kantoaaltovuotoa ja parillisia harmoonisia piirin lähdössä. Toinen integroitujen piirien vahvuus on kyky tarkkaan mikroaaltoalueen kvadratuurisignalointiin samalla piirillä, jolloin vältetään suurin osa kytkentöjen parasiittisista jotka muutoin voisivat tuhota korkeataajuuksisen 90-asteen vaiheistuksen. Kaikki kvadratuurimodulaattorit ovat joka tapauksessa herkkiä vaiheistus- ja amplitudieroille, joita syntyy komponenttiarvojen satunnaishajonnasta, epätarkan differentiaalisen signaloinnin käytöstä, ja itse vaiheistuspiiristön puutteellisuuksista. Kahden asteen vaihevirhe syntyy helposti, ja tällöin sivukaistavaimennus heikkenee -30 dBc:n tasolle. Tämänvuoksi, ja olettaen että digitaalisella signaaliprosessorilla luotu kantataajuuksinen signalointi on riittävän tarkkaa, tämä väitöskirja keskittyy kvadratuurimodulaattorin mikroaaltotaajuuksisen signaalipolun analysointiin ja tuottamiseen painottaen erityisesti laajakaistaista, monisovellusradioiden kanssa yhteensopivaa toimivuutta. Kvadratuurimodulaattorin toimintamallia on kehitetty siten, että mallissa huomioidaan epälineaarisuuksien ja piirielementtien satunnaishajontojen vaikutus saavutettavalle suorituskyvylle. Lisäksi on teoreettisesti todistettu sinänsä hyvin tunnettu peräkkäin kytkettyjen vahvistinasteiden differentiaalisen signaloinnin symmetrisyyttä parantava vaikutus. Käytännön tuloksista voidaan mainita kehitetty virtaakierrättävä sekoitin, joka parantaa signaali-kohinasuhdetta +3 dB, suurimman mitatun dynaamisen alueen ollessa +158 dB. Samaa komplementaarista bipolaariprosessia käytettiin edelleen bipolaarisen vuorovaihe-asteen kaistan levittämisessä 9.5 GHz:iin. Yhtenä tämän työn tärkeimmistä tuloksista on kehitetty kytkimin valittavista rinnakkaisista monivaihesuodattimista koostuva kvadratuurigeneraattori, jolla on mahdollista tuottaa laajakaistaista IQ-signalointia ilman suurta häviötä joka yleensä liittyy monivaihesuodattimien käyttöön. Kaksi IQ-modulaattoriprototyyppiä toteutettiin simuloitujen ja teoreettisesti mallinnettujen tulosten testaamiseksi: 0.8 µm SiGe integroitu piiri saavuttaa paremman sivukaistavaimennuksen kuin -40 dBc yli 0.75-3.6 GHz, kun taas 0.13 µm digitaalipiirien tuottamiseen tarkoitetulla CMOS prosessilla toteutettu integroitu piiri saavuttaa paremman sivukaistavaimennuksen kuin -37 dBc taajuusalueella 0.56-4.76 GHz. Näihin sivukaistavaimennuksiin SiGe prototyyppi pääsee edullisesti integroiduin symmetrointimuuntajin, kun taas CMOS piirillä käytetään kela-siirtojohto-tyyppistä yhdistelmämuuntajaa LO-sisääntulossa josta ajetaan erikseen kytkettäviä monivaihesuodattimia.reviewe

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Design of a 2.4 Ghz BAW-Based CMOS Transmitter

In recent years, bulk acoustic wave resonators (BAW) in combination with RF circuits have shown a big potential in achieving the low-power consumption and miniaturization level required to address wireless sensor nodes (WSN) applications. A lot of work has been focused on the receiver side, by integrating BAW resonators with low noise amplifiers (LNA) and in frequency synthesis with the design of BAW-based local oscillators, most of them working at fixed frequency due to their limited tuning range. At the architectural level, this has forced the implementation of several single channel transceivers. This thesis aims at exploring the use of BAW resonators in the transmitter, proposing an architecture capable of taking full advantage of them. The main objective is to develop a transmitter for WSN multi-channel applications able to cover the whole 2.4 GHz ISM band and enable the compatibility with wide-spread standards like Bluetooth and Bluetooth Low Energy. Typical transmissions should thus range from low data rates (typically tens of kb/s) to medium data rates (1 Mb/s), with FSK and GFSK modulation schemes, should be centered on any of the channels provided by these standards and cover a maximum transmission range of some tens of meters. To achieve these targets and circumvent the limited tuning range of the BAW oscillator, an up-conversion transmitter using wide IF is used. The typical spurs problems related to this transmitter architecture are addressed by using a combined suppression based on SSB mixing and selective amplification. The latter is achieved by cointegration of a high efficiency power amplifier with BAW resonators, which allows performing spurs filtering while preserving the efficiency. In particular the selective amplifier is designed by including in the PA analysis the BAW resonator parameters, which allows integrating the BAW filter into the passive network loading the amplifier, participating in the drain voltage shaping. Finally, the frequency synthesis section uses a fractional division plus LC PLL filtering and further integer division to generate the IF signals and exploit the very-low BAW oscillator phase noise. The transmitter has been integrated in a 0.18 µm standard digital CMOS technology. It allows addressing the whole 80 MHz wide 2.4 GHz ISM band. The unmodulated RF frequency carrier demonstrates a very-low phase noise of –136 dBc/Hz at 1 MHz offset. The IF spurs are maintained lower than –48 dBc, satisfying the international regulations for output power up to 10 dBm without the use of any quadrature error compensation in the transmitter. This is achieved thanks to the rejection provided by the SSB mixer and the selective amplifier, which can reach drain efficiency of up to 24% with integrated inductances, including the insertion losses of the BAW filter. The transmitter consumes 35.3 mA at the maximum power of 5.4 dBm under 1.6 V (1.2 V for the PA), while transmitting a 1 Mb/s GFSK signal and complying with both Bluetooth and Bluetooth Low Energy relative and absolute spectrum requirements

Continuous-time low-pass filters for integrated wideband radio receivers

This thesis concentrates on the design and implementation of analog baseband continuous-time low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work. After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator non-idealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations. Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-µm SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-µm and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the low-pass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a third-order 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented

Wideband Watt-Level Spatial Power-Combined Power Amplifier in SiGe BiCMOS Technology for Efficient mm-Wave Array Transmitters

The continued demand for high-speed wireless communications is driving the development of integrated high-power transmitters at millimeter wave (mm-Wave) frequencies. Si-based technologies allow achieving a high level of integration but usually provide insufficient generated RF power to compensate for the increased propagation and material losses at mm-Wave bands due to the relatively low breakdown voltage of their devices. This problem can be reduced significantly if one could combine the power of multiple active devices on each antenna element. However, conventional on-chip power combining networks have inherently high insertion losses reducing transmitter efficiency and limiting its maximum achievable output power.This work presents a non-conventional design approach for mm-Wave Si-based Watt-level power amplifiers that is based on novel power-combining architecture, where an array of parallel custom PA-cells suited on the same chip is interfaced to a single substrate integrated waveguide (to be a part of an antenna element). This allows one to directly excite TEm0 waveguide modes with high power through spatial power combining functionality, obviating the need for intermediate and potentially lossy on-chip power combiners. The proposed solution offers wide impedance bandwidth (50%) and low insertion losses (0.4 dB), which are virtually independent from the number of interfaced PA-cells. The work evaluates the scalability bounds of the architecture as well as discusses the critical effects of coupled non-identical PA-cells, which are efficiently reduced by employing on-chip isolation load resistors.The proposed architecture has been demonstrated through an example of the combined PA with four differential cascode PA-cells suited on the same chip, which is flip-chip interconnected to the combiner placed on a laminate. This design is implemented in a 0.25 um SiGe BiCMOS technology. The PA-cell has a wideband performance (38.6%) with both high peak efficiency (30%) and high saturated output power (24.9 dBm), which is the highest reported output power level obtained without the use of circuit-level power combining in Si-based technologies at Ka-band. In order to achieve the optimal system-level performance of the combined PA, an EM-circuit-thermal optimization flow has been proposed, which accounts for various multiphysics effects occurring in the joint structure. The final PA achieves the peak PAE of 26.7% in combination with 30.8 dBm maximum saturated output power, which is the highest achievable output power in practical applications, where the 50-Ohms load is placed on a laminate. The high efficiency (&gt;20%) and output power (&gt;29.8 dBm) over a wide frequency range (30%) exceed the state-of-the-art in Si-based PAs

Silicon Integrated Arrays: From Microwave to IR

Integrated chips have enabled realization and mass production of complex systems in a small form factor. Through process miniaturization many novel applications in silicon photonics and electronic systems have been enabled. In this thesis I have provided several examples of innovations that are only enabled by integration. I have also demonstrated how electronics and photonics circuits can complement each other to achieve a system with superior performance.</p