740 research outputs found
Single-input Multiple-output Tunable Log-domain Current-mode Universal Filter
This paper describes the design of a current-mode single-input multiple-output (SIMO) universal filter based on the log-domain filtering concept. The circuit is a direct realization of a first-order differential equation for obtaining the lossy integrator circuit. Lossless integrators are realized by log-domain lossy integrators. The proposed filter comprises only two grounded capacitors and twenty-four transistors. This filter suits to operate in very high frequency (VHF) applications. The pole-frequency of the proposed filter can be controlled over five decade frequency range through bias currents. The pole-Q can be independently controlled with the pole-frequency. Non-ideal effects on the filter are studied in detail. A validated BJT model is used in the simulations operated by a single power supply, as low as 2.5 V. The simulation results using PSpice are included to confirm the good performances and are in agreement with the theory
Concepts and methods in optimization of integrated LC VCOs
Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-μm MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results
34th Midwest Symposium on Circuits and Systems-Final Program
Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society.
Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi
ULTRA-LOW-JITTER, MMW-BAND FREQUENCY SYNTHESIZERS BASED ON A CASCADED ARCHITECTURE
Department of Electrical EngineeringThis thesis presents an ultra-low-jitter, mmW-band frequency synthesizers based on a cascaded
architecture. First, the mmW-band frequency synthesizer based on a CP PLL is presented. At the
first stage, the CP PLL operating at GHz-band frequencies generated low-jitter output signals due
to a high-Q VCO. At the second stage, an ILFM operating at mmW-band frequencies has a wide
injection bandwidth, so that the jitter performance of the mmW-band output signals is determined
by the GHz-range PLL. The proposed ultra-low-jitter, mmW-band frequency synthesizer based on
a CP PLL, fabricated in a 65-nm CMOS technology, generated output signals from GHz-band
frequencies to mmW-band frequencies, achieving an RMS jitter of 206 fs and an IPN of ???31 dBc.
The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively.
However, due to a large in-band phase noise contribution of a PFD and a CP in the CP PLL, this
first stage was difficult to achieve an ultra-low in-band phase noise. Second, to improve the in-band
phase noise further, the mmW-band frequency synthesizer based on a digital SSPLL is presented.
At the first stage, the digital SSPLL operating at GHz-band frequencies generated ultra-low-jitter
output signals due to its sub-sampling operation and a high-Q GHz VCO. To minimize the
quantization noise of the voltage quantizer in the digital SSPLL, this thesis presents an OSVC as a
voltage quantizer while a small amount of power was consumed. The proposed ultra-low-jitter,
mmW-band frequency synthesizer fabricated in a 65-nm CMOS technology, generated output
signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 77 fs
and an IPN of ???40 dBc. The active silicon area and the total power consumption were 0.32 mm2 and
42 mW, respectively.clos
An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers
Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThe rapid growth of wireless communications and the massive use of wireless end-user
equipments have created a demand for low-cost, low-power and low-area devices with
tight specifications imposed by standards. The advances in CMOS technology allows,
nowadays, designers to implement circuits that work at high-frequencies, thus, allowing
the complete implementation of RF front ends in a single chip.
In this work, a co-design strategy for the implementation of a fully integrated CMOS
receiver for use in the ISM band is presented. The main focus is given to the Mixer and
the ADC blocks of the presented architecture.
The traditional approach used in RF design requires 50
matching buffers and networks
and AC coupling capacitors between Mixer inputs and LNA and LO outputs. The codesign
strategy avoids the use of DC choke inductors for Mixer biasing, because it is
possible to use the DC level from the output of the LNA and the LO to provide bias to
the Mixer. Moreover, since the entire circuit is in the same chip and the Mixer inputs
are transistors gates, we should consider voltage instead of power and avoid the 50
matching networks.
The proposed ADC architecture relies on a 4-bit flash converter. The main goals are to
achieve low-power and high sampling frequency. To meet these goals, parametric amplification
based on MOS varactors is applied to reduce the offset voltage of the comparators,
avoiding the traditional and power-consuming approach of active pre-amplification gain
stages
A PLL frequency synthesizer for a 300 MHz high temperature transceiver realized in 0.5um SOS technology
This thesis presents a study of the design of a phase-lock loop (PLL) system, including specific designs for a voltage-controlled oscillator and programmable frequency divider, implemented in a 0.5μm silicon-on-sapphire CMOS technology. The system is designed for use as a frequency synthesizer in a high-temperature transceiver. Several issues relating to high-temperature applications as well as the overall system architecture are presented. Principles of the PLL system are described, and critical design considerations are discussed. The designs of the VCO and programmable divider are described and analyzed in detail. A brief discussion of the design and analysis of other PLL components is presented. Prototyping and testing procedures are discussed and the results of the prototyped circuits are evaluated. Finally, a summary of the work is presented along with insights gained toward future research
A MOSFET-only wideband LNA exploiting thermal noise canceling and gain optimization
Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresIn this thesis a MOSFET-only implementation of a balun LNA is presended. This LNA is
based on the combination of a common-gate and a common-source stage with canceling of
the noise of the common-gate stage. In this circuit, resistors are replaced by transistors,
to reduce area and cost, and minimize the e ect of process and supply variations and
mismatches. In addition we obtain a higher gain for the same voltage drop. Thus, the
LNA gain is optimized, and the noise gure(NF) is reduced. We derive equations for
the gain, input matching, and NF. The performance of this new topology is compared
with that of a conventional LNA with resistors. Simulation results with a 130 nm CMOS
technology show that we obtain a balun LNA with a peak 20.2 dB gain (about 2 dB
improvement), and a spot NF lower than 2.4 dB. The total power consumption is only
4.8 mW for a bandwidth wide than 5 GHz
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