A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

A multi-channel receiver operating between 56 GHz and 70 GHz for coverage of different 60 GHz bands worldwide is implemented with a 90 nm Complementary Metal-Oxide Semiconductor (CMOS) process. The receiver containing an LNA, a frequency down-conversion mixer and a variable gain amplifier incorporating a band-pass filter is designed and implemented. This integrated receiver is tested at four channels of centre frequencies 58.3 GHz, 60.5 GHz, 62.6 GHz and 64.8 GHz, employing a frequency plan of an 8 GHz-intermediate frequency (IF). The achieved conversion gain by coarse gain control is between 4.8 dB–54.9 dB. The millimeter-wave receiver circuit is biased with a 1.2V supply voltage. The measured power consumption is 69 mW

MIDAS: Automated Approach to Design Microwave Integrated Inductors and Transformers on Silicon

The design of modern radiofrequency integrated circuits on silicon operating at microwave and millimeter-waves requires the integration of several spiral inductors and transformers that are not commonly available in the process design-kits of the technologies. In this work we present an auxiliary CAD tool for Microwave Inductor (and transformer) Design Automation on Silicon (MIDAS) that exploits commercial simulators and allows the implementation of an automatic design flow, including three-dimensional layout editing and electromagnetic simulations. In detail, MIDAS allows the designer to derive a preliminary sizing of the inductor (transformer) on the bases of the design entries (specifications). It draws the inductor (transformer) layers for the specific process design kit, including vias and underpasses, with or without patterned ground shield, and launches the electromagnetic simulations, achieving effective design automation with respect to the traditional design flow for RFICs. With the present software suite the complete design time is reduced significantly (typically 1 hour on a PC based on Intel® Pentium® Dual 1.80GHz CPU with 2-GB RAM). Afterwards both the device equivalent circuit and the layout are ready to be imported in the Cadence environment

A 107GHz LNA in 65nm CMOS with inductive neutralization and slow-wave transmission lines

This paper presents a 107GHz LNA prototype using TSMC 65nm CMOS technology. It explores the limit of the CMOS technology by effectively optimizing the active and passive devices. An improvement of 1.6dB higher maximum stable/available gain (MSG/MAG) on the transistor is achieved around 110GHz by layout optimization and inductor neutralization technique. A high quality factor co-planar waveguide (CPW) transmission line is designed utilizing the slow-wave effect. A quality factor of 23.6 is demonstrated by EM-simulations while taken the consideration of satisfying the stringent layout design rules. Based on the optimization on the active and passive devices, a dual-stage LNA is designed, with a simulated power gain of 10.2dB and noise figure of 8dB at 107GHz, verified by chip-level EM-simulations. The power consumption is 28.2mW

Design methods for 60GHz beamformers in CMOS

The 60GHz band is promising for applications such as high-speed short-range wireless personal-area network (WPAN), real-time video streaming at rates of several-Gbps, automotive radar, and mm-Wave imaging, since it provides a large amount of bandwidth that can freely (i.e. without a license) be used worldwide. However, transceivers at 60GHz pose several additional challenges over microwave transceivers. In addition to the circuit design challenges of implementing high performance 60GHz RF circuits in mainstream CMOS technology, the path loss at 60GHz is significantly higher than at microwave frequencies because of the smaller size of isotropic antennas. This can be overcome by using phased array technology. This thesis studies the new concepts and design techniques that can be used for 60GHz phased array systems. It starts with an overview of various applications at mm-wave frequencies, such as multi-Gbps radio at 60GHz, automotive radar and millimeter-wave imaging. System considerations of mm-wave receivers and transmitters are discussed, followed by the selection of a CMOS technology to implement millimeter-wave (60GHz) systems. The link budget of a 60GHz WPAN is analyzed, which leads to the introduction of phased array techniques to improve system performance. Different phased array architectures are studied and compared. The system requirements of phase shifters are discussed. Several types of conventional RF phase shifters are reviewed. A 60GHz 4-bit passive phase shifter is designed and implemented in a 65nm CMOS technology. Measurement results are presented and compared to published prior art. A 60GHz 4-bit active phase shifter is designed and integrated with low noise amplifier and combiner for a phased array receiver. This is implemented in a 65nm CMOS technology, and the measurement results are presented. The design of a 60GHz 4-bit active phase shifter and its integration with power amplifier is also presented for a phased array transmitter. This is implemented in a 65nm CMOS technology. The measurement results are also presented and compared to reported prior art. The integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package is investigated. Experimental results are presented and discussed

Design And Implementation Of Millimeter Wave Frequency Multiplier In 65Nm Rf Cmos Technology

In this thesis, the design and implementation of frequency multipliers in 65nm CMOS was explored for millimeter wave oscillators and optimized to achieve higher output power and better rejection of the fundamental frequency. Several types of frequency multipliers are discussed. Transformers for AC-coupling used in the frequency multipliers were also explored. The design and optimization of the circuits was performed using Sonnet, Cadence, and ADS software tools. In this work the design of a frequency multiplier which takes in a 12.5GHz signal and outputs 100GHz at the output is achieved. Three transformers are used for three stages of a frequency doubler to achieve a multiplication by eight. High isolation is achieved between the input frequency and the output. The output power level is –4dBm. The fundamental rejection is above 35dB. The power consumed by this frequency multiplier is 18mW. While multiplication of up to 4 is achieved in CMOS devices in other works, we are able to achieve a frequency multiplication of 8 in this work

Design And Implementation Of Millimeter Wave Frequency Multiplier In 65Nm Rf Cmos Technology

In this thesis, the design and implementation of frequency multipliers in 65nm CMOS was explored for millimeter wave oscillators and optimized to achieve higher output power and better rejection of the fundamental frequency. Several types of frequency multipliers are discussed. Transformers for AC-coupling used in the frequency multipliers were also explored. The design and optimization of the circuits was performed using Sonnet, Cadence, and ADS software tools. In this work the design of a frequency multiplier which takes in a 12.5GHz signal and outputs 100GHz at the output is achieved. Three transformers are used for three stages of a frequency doubler to achieve a multiplication by eight. High isolation is achieved between the input frequency and the output. The output power level is –4dBm. The fundamental rejection is above 35dB. The power consumed by this frequency multiplier is 18mW. While multiplication of up to 4 is achieved in CMOS devices in other works, we are able to achieve a frequency multiplication of 8 in this work

Digitally Controlled Oscillator for mm-Wave Frequencies

In the fifth generation of mobile communication, 5G, frequencies above 30 GHz, so-called millimeter-wave (mm-wave) frequencies are expected to play a prominent role. For the synthesis of these frequencies, the all-digital phase locked loop (ADPLL) has recently gained much attention. A core component of the ADPLL is the digitally controlled oscillator (DCO), an oscillator that tunes the frequency discretely. For good performance, the frequency steps must be made very small, while the total tuning range must be large. This thesis covers several coarse- and fine-tuning techniques for DCOs operating at mm-wave frequencies. Three previously not published fine-tuning schemes are presented: The first one tunes the second harmonic, which will, due to the Groszkowski effect, tune the fundamental tone. The second one is a current-modulation scheme, which utilizes the weak current-dependence of the capacitance of a transistor to tune the frequency. In the third one, a digital-to-analog converter (DAC) is connected to the bulk of the differential pair and tunes the frequency by setting the bulk voltage. The advantages and disadvantages of the presented tuning schemes are discussed and compared with previously reported fine-tuning schemes. Two oscillators were implemented at 86 GHz. Both oscillator use the same oscillator core and hence have the same power consumption and tuning range, 14.1 mW and 13.9%. A phase noise of -89.7 dBc/Hz and -111.4 dBc/Hz at 1 MHz and 10 MHz offset, respectively, were achieved, corresponding to a Figure-of-Merit of -178.5 dBc/Hz. The first oscillator is fine-tuned using a combination of a transformer-based fine-tuning and the current modulation scheme presented here. The achieved frequency resolution is 55 kHz, but can easily be made finer. The second oscillator utilizes the bulk bias technique to achieve its fine tuning. The fine-tuning resolution is here dependent on the resolution of the DAC; a 100μV resolution corresponds to a resolution of 50 kHz.n 2011, the global monthly mobile data usage was 0.5 exabytes, or 500 million gigabytes. In 2016, this number had increased to 7 exabytes, an increase by a factor 14 in just five years, and there are no signs of this trend slowing down. To meet the demands of the ever increasing data usage, engineers have begun to investigate the possibility to use significantly higher frequencies, 30 GHz or higher, for mobile communication than what is used today, which is 3 GHz or below. To be able to transmit and receive data at these high frequency, an oscillator capable of operating at these frequencies are required. An oscillator is an electrical circuit that generates an alternating current (a current that first goes one way, and then the other) at a specific frequency. Below is an example to illustrate to function and importance of the oscillator: Imagine driving a car and listening to the radio. Suddenly, a horrendous song starts playing from the radio, so you instantly tune to another station and find some great, smooth jazz. Satisfied, you lean back and drive on. But what exactly happened when you "tuned to another station"? What you really did was changing the frequency of the oscillator, which can be found in the radio receiver of the car. The radio receiver filters out all frequencies, except for the frequency of the local oscillator. So by setting the frequency of the local oscillator to the frequency of the desired radio channel, only this radio channel will reach the speakers of the car. Thus, the oscillator must be able to vary its frequency to any frequency that a radio station can transmit on. While an old car radio may seem like a simple example, the very same principle is used in mobile communication, even at frequencies above 30 GHz. The oscillator is also used in the same way when transmitting signals, so that the signals are transmitted on the correct frequency. The design of the local oscillator is a hot topic among radio engineers. A poorly designed oscillator will ruin the performance of the whole receiver or transmitter. This thesis covers the design of a special type of oscillators, called digital controlled oscillators or DCO, operating at 30 GHz or higher. The frequency of these oscillators are determined by a digital word (ones and zeros), instead of using an analog voltage, which is traditionally used. Digital control results in greater flexibility and higher noise-resilience, but it also means that the frequency can’t be changed continuously, but rather in discrete steps. This discrete behavior will cause noise in the receiver. To minimize this noise, the frequency steps should be minimized. In this thesis, we have proposed a DCO design, operating at 85.5 GHz, which can be tuned almost 7 % in either direction. To our knowledge, no other DCO operates at such high frequencies. In the proposed oscillators the frequency steps are only 55 kHz apart, which is so small that its effect on the radio receiver can, with a good conscience, be ignored. This is achieved with a novel technique that makes tiny, tiny changes in the current that passes through the oscillator

Design of injection locked frequency divider in 65nm CMOS technology for mmW applications

In this paper, an Injection Locking Frequency Divider (ILFD) in 65 nm RF CMOS Technology for applications in millimeter-wave (mm-W) band is presented. The proposed circuit achieves 12.69% of locking range without any tuning mechanism and it can cover the entire mm-W band in presence of Process, Voltage and Temperature (PVT) variations by changing the Injection Locking Oscillator (ILO) voltage control. A design methodology flow is proposed for ILFD design and an overview regarding CMOS capabilities and opportunities for mm-W transceiver implementation is also exposed.Postprint (published version