31 research outputs found
Microgrid - The microthreaded many-core architecture
Traditional processors use the von Neumann execution model, some other
processors in the past have used the dataflow execution model. A combination of
von Neuman model and dataflow model is also tried in the past and the resultant
model is referred as hybrid dataflow execution model. We describe a hybrid
dataflow model known as the microthreading. It provides constructs for
creation, synchronization and communication between threads in an intermediate
language. The microthreading model is an abstract programming and machine model
for many-core architecture. A particular instance of this model is named as the
microthreaded architecture or the Microgrid. This architecture implements all
the concurrency constructs of the microthreading model in the hardware with the
management of these constructs in the hardware.Comment: 30 pages, 16 figure
SL: a "quick and dirty" but working intermediate language for SVP systems
The CSA group at the University of Amsterdam has developed SVP, a framework
to manage and program many-core and hardware multithreaded processors. In this
article, we introduce the intermediate language SL, a common vehicle to program
SVP platforms. SL is designed as an extension to the standard C language (ISO
C99/C11). It includes primitive constructs to bulk create threads, bulk
synchronize on termination of threads, and communicate using word-sized
dataflow channels between threads. It is intended for use as target language
for higher-level parallelizing compilers. SL is a research vehicle; as of this
writing, it is the only interface language to program a main SVP platform, the
new Microgrid chip architecture. This article provides an overview of the
language, to complement a detailed specification available separately.Comment: 22 pages, 3 figures, 18 listings, 1 tabl
MGSim - Simulation tools for multi-core processor architectures
MGSim is an open source discrete event simulator for on-chip hardware
components, developed at the University of Amsterdam. It is intended to be a
research and teaching vehicle to study the fine-grained hardware/software
interactions on many-core and hardware multithreaded processors. It includes
support for core models with different instruction sets, a configurable
multi-core interconnect, multiple configurable cache and memory models, a
dedicated I/O subsystem, and comprehensive monitoring and interaction
facilities. The default model configuration shipped with MGSim implements
Microgrids, a many-core architecture with hardware concurrency management.
MGSim is furthermore written mostly in C++ and uses object classes to represent
chip components. It is optimized for architecture models that can be described
as process networks.Comment: 33 pages, 22 figures, 4 listings, 2 table