Graph model analysis of computer structures

Graph theory is applicable to the solving of problems in nearly every field of scientific study. The purpose of this thesis is to consider its applications in representing and analyzing digital computers. Fundamental graph theory definitions, the types and the properties of the directed graphs, the matrix representation, and several reduction techniques are discussed. The blocking gate method for diagnosing computer systems is described and applied to the Scientific Control Corporation (SCC) 650 for its fault-diagnosis. Microprogramming has been a significant trend in hardware and software designs of computers. Microprogrammed computers are discussed in comparison to conventional computers. A general scheme utilizing four nodes generates directed graphs for both types of architecture. The directed graphs are studied with respect to the flexibility and cost parameters --Abstract, page ii

Hybrid receiver study

The results are presented of a 4 month study to design a hybrid analog/digital receiver for outer planet mission probe communication links. The scope of this study includes functional design of the receiver; comparisons between analog and digital processing; hardware tradeoffs for key components including frequency generators, A/D converters, and digital processors; development and simulation of the processing algorithms for acquisition, tracking, and demodulation; and detailed design of the receiver in order to determine its size, weight, power, reliability, and radiation hardness. In addition, an evaluation was made of the receiver's capabilities to perform accurate measurement of signal strength and frequency for radio science missions

Autonomous navigation accuracy using simulated horizon sensor and sun sensor observations

A relatively simple autonomous system which would use horizon crossing indicators, a sun sensor, a quartz oscillator, and a microprogrammed computer is discussed. The sensor combination is required only to effectively measure the angle between the centers of the Earth and the Sun. Simulations for a particular orbit indicate that 2 km r.m.s. orbit determination uncertainties may be expected from a system with 0.06 deg measurement uncertainty. A key finding is that knowledge of the satellite orbit plane orientation can be maintained to this level because of the annual motion of the Sun and the predictable effects of Earth oblateness. The basic system described can be updated periodically by transits of the Moon through the IR horizon crossing indicator fields of view

Telecommunications Hardware and Software Systems made in CMEA Countries and Yugoslavia

The telecommunications hardware and software systems used in CMEA (Council of Mutual Economic Assistance) countries and Yugoslavia are a most complex field of investigation. For this reason in this study the following approach has been adopted: Rather than collecting and presenting all CMEA telecommunications hardware and software systems in a directory type of form, which would neither be complete nor fully up to date (even at the time of data collection), a general analysis is given, with sufficient detailed information to make it useful. During the analysis we will discuss in depth the different classes of telecommunications hardware and software systems, their past, present, and potential future. In order to do this, the analysis has to include all major levels of the International Standardization Organization's Open System Interconnection (ISO/OSI) Reference Model--and this is the way we handle the telecommunications hardware and software systems of the CMEA countries and of Yugoslavia

CAMAC bulletin: A publication of the ESONE Committee Issue #13 September 1975 Supplement B

CAMAC is a means of interconnecting many peripheral devices through a digital data highway to a data processing device such as a computer

Aerospace Applications of Microprocessors

An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed

Timing Architecture for ESS

Programa Oficial de Doutoramento en Investigación en Tecnoloxías da Información. 5023V01[Resumo] O sistema de temporización é unha compoñente fundamental para o control e sincronización de instalacións industriais e científicas, coma aceleradores de partículas. Nesta tese traballamos na especificación e desenvolvemento do sistema de temporización para a European Spallation Source (ESS), a maior fonte de neutróns actualmente en construción. Abordamos este tra­ ballo a dous niveis: a especificación do sistema de temporización, e a imple­ mentación física de sistemas de control empregando circuítos reconfigurables. Con respecto á especificación do sistema de temporización, deseñamos e implementamos a configuración do protocolo de temporización para cumprir cos requirimentos do ESS e ideamos un modo de operación e unha aplicación para a configuración e control do sistema de temporización. Tamén presentamos unha ferramenta e unha metodoloxía para imple­ mentar sistemas de control empregando FPGAs, coma os nodos do sistema de temporización. ámbalas <lúas están baseadas en statecharts, unha repre­ sentación gráfica de sistemas que expande o concepto de máquinas de estados finitos, orientada a sistemas que necesitan ser reconfigurados rápidamente en múltiples localizacións minimizando a posibilidade de erros. A ferramenta crea automaticamente código VHDL sintetizable a partir do statechart do sistema. A metodoloxía explica o procedemento para implementar o state­ chart como unha arquitectura microprogramada en FPGAs.[Resumen] El sistema de temporización es un componente fundamental para el control y sincronización de instalaciones industriales y científicas, como aceleradores e partículas. En esta tesis trabajamos en la especificación y desarrollo el sistema de temporización para la European Spallation Source (ESS), la mayor fuente de neutrones actualmente en construcción. Abordamos este trabajo en dos niveles: la especificación del sistema de temporización, y la mplementación física de sistemas de control empleando circuitos reconfig­ rables. Con respecto a la especificación del sistema de temporización, diseñamos e implementamos la configuración del protocolo de temporización para cumplir on los requisitos de ESS e ideamos un modo de operación y una aplicación ara la configuración y control del sistema de temporización. También presentamos una herramienta y una metodología para imple­ entar sistemas de control empleando FPGAs, como los nodos del sistema e temporización. Ambas están basadas en statecharts) una representación gráfica de sistemas que expande el concepto de máquinas de estados fini­ os, orientada a sistemas que necesitan ser reconfigurados rápidamente en últiples localizaciones minimizando la posibilidad de errores. La her­ramienta crea automáticamente código VHDL sintetizable a partir del state­chart del sistema. La metodología explica el procedimiento para implemen­tar el statechart como una arquitectura microprogramada en FPGAs.[Abstract] The timing system is a key component for the control and synchronization of industrial and scientific facilities, such as particle accelerators. In this thesis we tackle the specification and development of the timing system for the European Spallation Source (ESS), the largest neutron source currently in construction. We approach this work at two levels: the specification of the timing system and the physical implementation of control systems using reconfigurable hardware. Regarding the specification of the timing system, we designed and imple­ mented the configuration of the timing protocol to fulfil the requirements of ESS and devised an operation mode andan application for the configuration and control of the timing system. We also present one too! and one methodology to implement control systems using FPGAs, such as the nodes of the timing system. Both are based on statecharts, a graphical representation of systems that expand the concepts of Finite State Machines, targeted at systems that need to be re­ configured quickly in multiple locations minimizing the chance of errors. The too! automatically creates synthesizable VHDL code from a statechart of the system. The methodology explains the procedure to implement the statechart as a microprogrammed architecture in FPGAs

A high level disc controller

Includes bibliographical references.Since the emergence of the digital computer in the 1940s, computer architecture has been largely dictated by the requirements of mathematicians and scientists. Trends have thus been towards processing data as quickly and as accurately as possible. Even now, in the age of large scale integration culminating in the microprocessor, internal structures remain committed to these ideals. This is not surprising since the main users of computers are involved with data processing and scientific computing. The process control engineer, who turned to the digital computer to provide the support he required in his ever increasing strive towards automation, has had therefore to use these generalized computing structures. His basic requirements however, are somewhat different to those of the data processing manager or the scientific user. He has to contend with an inherent problem of synchronizing the computer to the real-world timing of his plants. He is far more interested in the response time of the computer to an external occurrence than he is to sheer 'number-crunching' power. Despite the trends in process control towards distributed computing, even the most advanced systems require a relatively large central processor. This processor is called upon to carry out a wide variety of different tasks most of which are 'requested' by external events. Multiprogramming facilities are therefore essential and are normally effected by means of a real-time operating system. One of the prime objectives of such a real time operating system is to permit the various programs to be run at the required time on some priority basis. In many cases these routines can be large - thus requiring access to backing storage. Traditionally the backing store, implemented by a moving-head disc for example is under the control of the real-time operating system. This can have serious consequences. If real-time requirements are to be met, transfer to and from the disc must be made as rapidly as possible. Also, in initiating and controlling such transfer, the computer is using time which otherwise could be avai1ab1e for useful, process-orientated work. With the rapid advancement of digital technology, the time is c1ear1y right to examine our present computer architecture. This dissertation explores the problem area previously discussed - the control over the bulk storage device in a real-time process-control computer system. It is proposed that a possible solution lies in the development of an intelligent backing-store controller. This essentially combines the conventional low-level backing store interface with a special purpose processor which handles all file routines. This dissertation demonstrates how such a structure can be implemented using current technology, and will evaluate its inherent advantages