On-Line Instruction-checking in Pipelined Microprocessors

Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instruction

The AXIOM software layers

AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).The Software Layers developed at the AXIOM project are explained.OmpSs provides an easy way to execute heterogeneous codes in multiple cores. People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed.The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics).Peer ReviewedPostprint (author's final draft

Static locality analysis for cache management

Most memory references in numerical codes correspond to array references whose indices are affine functions of surrounding loop indices. These array references follow a regular predictable memory pattern that can be analysed at compile time. This analysis can provide valuable information like the locality exhibited by the program, which can be used to implement more intelligent caching strategy. In this paper we propose a static locality analysis oriented to the management of data caches. We show that previous proposals on locality analysis are not appropriate when the proposals have a high conflict miss ratio. This paper examines those proposals by introducing a compile-time interference analysis that significantly improve the performance of them. We first show how this analysis can be used to characterize the dynamic locality properties of numerical codes. This evaluation show for instance that a large percentage of references exhibit any type of locality. This motivates the use of a dual data cache, which has a module specialized to exploit temporal locality, and a selective cache respectively. Then, the performance provided by these two cache organizations is evaluated. In both organizations, the static locality analysis is responsible for tagging each memory instruction accordingly to the particular type(s) of locality that it exhibits.Peer ReviewedPostprint (published version

Chaos in computer performance

Modern computer microprocessors are composed of hundreds of millions of transistors that interact through intricate protocols. Their performance during program execution may be highly variable and present aperiodic oscillations. In this paper, we apply current nonlinear time series analysis techniques to the performances of modern microprocessors during the execution of prototypical programs. Our results present pieces of evidence strongly supporting that the high variability of the performance dynamics during the execution of several programs display low-dimensional deterministic chaos, with sensitivity to initial conditions comparable to textbook models. Taken together, these results show that the instantaneous performances of modern microprocessors constitute a complex (or at least complicated) system and would benefit from analysis with modern tools of nonlinear and complexity science

The FTC's Challenge to Intel's Cross-Licensing Practices

After an investigation lasting several months, in June 1998 the Federal Trade Commission brought an antitrust lawsuit against Intel Corporation based on Intel's conduct towards Intergraph, and similar conduct towards Digital Equipment Corporation and Compaq, all in the context of disputes where Intel was accused of patent infringement. The FTC charged that Intel's practices were an abuse of Intel's monopoly position in microprocessors. Is Intel's conduct anti-competitive and thus illegal under the antitrust laws? That is the central question explored in this paper. An introductory section provides some background for the case by discussing the tension between intellectual property rights and antitrust law, a tension that is evident in the FTC's dispute with Intel, and by describing the role of patents in the semiconductor industry. Section 3 provides a succinct summary of the facts surrounding Intel's conduct in each of the three patent disputes identified by the FTC. Section 4 explains the FTC's theory of how Intel's conduct was anti-competitive. Section 5 presents Intel's response. Section 6 describes the settlement reached between the FTC and Intel. The final section discusses legal and economic developments since the case was settled and remarks on the lasting implications of the Intel case.

Application of active control landing gear technology to the A-10 aircraft

Two concepts which reduce the A-10 aircraft's wing/gear interface forces as a result of applying active control technology to the main landing gear are described. In the first concept, referred to as the alternate concept a servovalve in a closed pressure control loop configuration effectively varies the size of the third stage spool valve orifice which is embedded in the strut. This action allows the internal energy in the strut to shunt hydraulic flow around the metering orifice. The command signal to the loop is reference strut pressure which is compared to the measured strut pressure, the difference being the loop error. Thus, the loop effectively varies the spool valve orifice size to maintain the strut pressure, and therefore minimizes the wing/gear interface force referenced

EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards

Evaluating the faulty behavior of low-cost embedded microprocessor-based boards is an increasingly important issue, due to their adoption in many safety critical systems. The architecture of a complete Fault Injection environment is proposed, integrating a module for generating a collapsed list of faults, and another for performing their injection and gathering the results. To address this issue, the paper describes a software-implemented Fault Injection approach based on the Trace Exception Mode available in most microprocessors. The authors describe EXFI, a prototypical system implementing the approach, and provide data about some sample benchmark applications. The main advantages of EXFI are the low cost, the good portability, and the high efficienc