Re-Engineering of the CERN Accelerators and Services Control System based on VMEbus and PowerPC Technology

A new generation of PowerPC VMEbus front-end computers is being introduced in the CERN accelerators and services control system infrastructure. This new technology is aimed at replacing existing PC based front-end computers and at offering a high performance microprocessor platform for present and future engineering developments for the LHC era. This paper describes the re-engineering strategy and the core architecture of the new systems. Special performance issues are also addressed in this paper

Firm Capabilities, Competition and Industrial Policies in a History-Friendly Model of the Computer Industry

In this paper, we explore some problems that industrial policy faces in industries characterized by dynamic increasing returns on the basis of a 'history friendly model' of the evolution of the computer industry. How does policy affect industry structure over the course of industry evolution? Is the timing of the intervention important? Do policy interventions have indirect and perhaps unintended consequences on different markets at different times? We focus on two sets of policies: antitrust and interventions aiming at supporting the entry of new forms in the industry. The results of our simulations show that, if strong dynamic increasing returns are operative, both through technological capabilities and through customer tendency to stick with a brand, there is little that antitrust and entry policy could have done to avert the rise of a dominant firm in mainframes. On the other hand, if the customer lock in effect had been smaller, either by chance or through policies that discouraged efforts of firms to lock in their customers, the situation might have been somewhat different. In the first place, even in the absence of antitrust or entry encouraging policies, market concentration would have been lower, albeit a dominant firm would emerge anyhow. Second, antitrust and entry encouraging policies would have been more effective in assuring that concentration would decrease. The leading firm would continue to dominate the market, but its relative power would be reduced. © Elsevier Science B.V

Multicomputer communication system

A local area network is provided for a plurality of autonomous computers which operate at different rates and under different protocols coupled by network bus adapters to a global bus. A host computer (HC) divides a message file to be transmitted into blocks, each with a header that includes a data type identifier and a trailer. The associated network bus adapter (NBA) then divides the data into packets, each with a header to which a transport header and trailer is added with frame type code which specifies one of three modes of addressing in the transmission of data, namely a physical address mode for computer to computer transmission using two bytes for source and destination addresses, a logical address mode and a data type mode. In the logical address mode, one of the two addressing bytes contains a logical channel number (LCN) established between the transmitting and one or more receiving computers. In the data type mode, one of the addressing bytes contains a code identifying the type of data

Count three for wear able computers

This paper is a postprint of a paper submitted to and accepted for publication in the Proceedings of the IEE Eurowearable 2003 Conference, and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library. A revised version of this paper was also published in Electronics Systems and Software, also subject to Institution of Engineering and Technology Copyright. The copy of record is also available at the IET Digital Library.A description of 'ubiquitous computer' is presented. Ubiquitous computers imply portable computers embedded into everyday objects, which would replace personal computers. Ubiquitous computers can be mapped into a three-tier scheme, differentiated by processor performance and flexibility of function. The power consumption of mobile devices is one of the most important design considerations. The size of a wearable system is often a design limitation

Vertical Integration and Dis-integration of Computer Firms: A History Friendly Model of the Co-evolution of the Computer and Semiconductor Industries

In this paper we present a history-friendly model of the changing vertical scope of computer firms during the evolution of the computer and semiconductor industries. The model is "history friendly", in that it attempts at replicating some basic, stylized qualitative features of the evolution of vertical integration on the basis of the causal mechanisms and processes which we believe can explain the history. The specific question addressed in the model is set in the context of dynamic and uncertain technological and market environments, characterized by periods of technological revolutions punctuating periods of relative technological stability and smooth technical progress. The model illustrates how the patterns of vertical integration and specialization in the computer industry change as a function of the evolving levels and distribution of firms' capabilities over time and how they depend on the co-evolution of the upstream and downstream sectors. Specific conditions in each of these markets - the size of the external market, the magnitude of the technological discontinuities, the lock-in effects in demand - exert critical effects and feedbacks on market structure and on the vertical scope of firms as time goes by

Adaptive Latency Insensitive Protocols

Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. It achieves its goal via encapsulation of synchronous logic blocks in wrappers that communicate through a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from an excessive performance penalty in terms of throughput or from a lack of generality. This article presents an adaptive LIP that outperforms previous static implementations, as demonstrated by two relevant cases — a microprocessor and an MPEG encoder — whose components we made insensitive to the latencies of their interconnections through a newly developed wrapper. We also present an informal exposition of the theoretical basis of adaptive LIPs, as well as implementation detail

On-Line Instruction-checking in Pipelined Microprocessors

Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instruction