Bipolar Bit Slice Microprocessors

The purpose of this paper is to undertake a survey of state of the art high speed bipolar bit slice microprocessor elements. Three systems are discussed: The 2900 microprocessor family; the 10800 microprocessor family and the 8X02 microcontroller. A description of the microprocessor and microprogram controller elements for each family is presented and an example of the 2900 family is discussed

Micro-threading and FPGA implementation of a RISC microprocessor : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science at Massey University, Palmerston North, New Zealand

Appendix E removed due to copyright restrictions. Articles are available in the print copy held in the libraryThis thesis is the outcome of research in two areas of computer technology: microprocessor and multi-processor architectures (specifically from the perspective of how differently they tolerate highly-latent and non-deterministic events), and hardware design of complex digital systems containing both datapath and control (particularly microprocessors). This thesis starts by pointing out that in order to achieve high processing speeds, current popular superscalar microprocessors (e.g. Intel Pentiums, Digital Alpha, etc) rely heavily on the technique of speculating the outcome of instruction flow in order to predict the behaviour of non-deterministic computing operations (as in loading operands from high-latency memory into the processor). This is fine only if the speculation is correct. But, what if it isn't? If the speculation fails, this would mean that the processor has to abandon its current decision (which now proved to be the wrong one) for the instruction flow path taken and to start all over again with the other path (the actual correct one). This is a waste of valuable processing time and hardware resources and a reduction of performance when speculation fails. Therefore, these processors can achieve high performance only when the majority of speculations are successful (being able to predict the right path). In an attempt to overcome the above shortcomings, the first part of this thesis is an investigation of the novel vector micro-threading architecture as an alternative approach to the current superscalar-based speculative microprocessor designs. Micro-threading is based on the not-so-novel multithreading technique, which avoids speculation altogether and instead, starts running a different thread of instructions while waiting for the non-determinism to be resolved. This utilizes the chip resources more efficiently without waste of any processing power. The rest of this thesis focuses on the baseline RISC processor platform, the MIPS R2000, which is reviewed first then partially synthesized from the RTL (Register Transfer Level) description using VHDL and then simulated and tested. This is conducted in order for future research to build upon and add the micro-threading architectural add-ons and modifications. Keywords: Micro-threading, Latency Tolerance, FPGA Synthesis, RISC Architecture, MIPS R2000 processor, VHDL

On-Line Sea Beam Acoustic Imaging

This paper describes a system designed and built at the Marine Physical Laboratory of the Scripps Institution of Oceanography to produce acoustic images of the seafloor on-line with a Sea Beammultibeam echo-sounder. This system uses a stand alone interface between the Sea Beam system and a grey-scale line-scan recorder. The interface is built around a Motorola 68000 microprocessor and has digitizing capabilities. It digitizes the detected echo signals from each of the 16 preformed beams inside the Sea Beam echo processor as well as the roll information given by the ship\u27s vertical reference. Theacoustic data are then roll compensated and combined into a port and a starboard time series. These time series are eventually output in digital format to a line-scan recorder which produces the grey scaleacoustic image. Results are discussed for Sea Beam acoustic images of the seafloor and of the Deep Scattering layers

EMULATION TOOL FOR TESTING FAULT TOLERANCE

The aim of this paper is to show a possible adaptation of the well known microprocessor emulation method for testing fault tolerance, and to examine the advantages of the adap-tation. First a survey on test methods and their application will be given with respect to the possibilities for testing fault tolerant architectures. It will be followed by a short overview of different microprocessor fault models, and the fault injection routines based on the fault models. The injection routines require some hardware extension of the con-ventional microprocessor in-circuit emulator. The necessary extensions are shown on a MC68000 based in-circuit emulator. Finally, some improvement possibilities are discussed

Modifications and Improvements to the Sea Beam System on Board R/V Thomas Washington

A number of modifications to the narrowbeam echo-sounder and echo processor of the Sea Beammultibeam bathymetric survey system have been implemented. These include the design and construction of a digital pitch compensator, the ability to use a variety of sensors for vertical reference, the design and construction of hardware test equipment, and an interface to the shipboard DEC VAX-11/730 computer for data logging, automation of start-up procedures, and performance monitorin

Microprogramming and microprocessors in the Netherlands

This paper gives a short survey of the activities in the field of microprocessors and microprogramming in the Netherlands. In the first part of it the activies within the Universities and non commercial institutes are mentioned. The second part deals with the industrial activity. The author is aware of the incompleteness of the survey. The reason for it is twofold. First; Some of the activies, especially in the industrie, have confidential aspects. The information may not yet appear in a paper like this. Second; He is not aware of all activities carried out in the field. A list of names of the institutes etcand eventual contactpersons is included. A literature list is not added, because not much literature is available now

On-Line Instruction-checking in Pipelined Microprocessors

Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instruction

Satellite on-board processing for earth resources data

Results of a survey of earth resources user applications and their data requirements, earth resources multispectral scanner sensor technology, and preprocessing algorithms for correcting the sensor outputs and for data bulk reduction are presented along with a candidate data format. Computational requirements required to implement the data analysis algorithms are included along with a review of computer architectures and organizations. Computer architectures capable of handling the algorithm computational requirements are suggested and the environmental effects of an on-board processor discussed. By relating performance parameters to the system requirements of each of the user requirements the feasibility of on-board processing is determined for each user. A tradeoff analysis is performed to determine the sensitivity of results to each of the system parameters. Significant results and conclusions are discussed, and recommendations are presented