Optimal edge termination for high oxide reliability aiming 10kV SiC n-IGBTs

The edge termination design strongly affects the ability of a power device to support the desired voltage and its reliable operation. In this paper we present three appropriate termination designs for 10kV n-IGBTs which achieve the desired blocking requirement without the need for deep and expensive implantations. Thus, they improve the ability to fabricate, minimise the cost and reduce the lattice damage due to the high implantation energy. The edge terminations presented are optimised both for achieving the widest immunity to dopant activation and to minimise the electric field at the oxide. Thus, they ensure the long-term reliability of the device. This work has shown that the optimum design for blocking voltage and widest dose window does not necessarily give the best design for reliability. Further, it has been shown that Hybrid Junction Termination Extension structure with Space Modulated Floating Field Rings can give the best result of very high termination efficiency, as high as 99%, the widest doping variation immunity and the lowest electric field in the oxide

Automatic programming methodologies for electronic hardware fault monitoring

This paper presents three variants of Genetic Programming (GP) approaches for intelligent online performance monitoring of electronic circuits and systems. Reliability modeling of electronic circuits can be best performed by the Stressor - susceptibility interaction model. A circuit or a system is considered to be failed once the stressor has exceeded the susceptibility limits. For on-line prediction, validated stressor vectors may be obtained by direct measurements or sensors, which after pre-processing and standardization are fed into the GP models. Empirical results are compared with artificial neural networks trained using backpropagation algorithm and classification and regression trees. The performance of the proposed method is evaluated by comparing the experiment results with the actual failure model values. The developed model reveals that GP could play an important role for future fault monitoring systems.This research was supported by the International Joint Research Grant of the IITA (Institute of Information Technology Assessment) foreign professor invitation program of the MIC (Ministry of Information and Communication), Korea

NASA guidelines on report literature

NASA seeks for inclusion in its Scientific and Technical Information System research reports, conference proceedings, meeting papers, monographs, and doctoral and post graduate theses which relate to the NASA mission and objectives. Topics of interest to NASA are presented

Resonance Damping in Ferromagnets and Ferroelectrics

The phenomenological equations of motion for the relaxation of ordered phases of magnetized and polarized crystal phases can be developed in close analogy with one another. For the case of magnetized systems, the driving magnetic field intensity toward relaxation was developed by Gilbert. For the case of polarized systems, the driving electric field intensity toward relaxation was developed by Khalatnikov. The transport times for relaxation into thermal equilibrium can be attributed to viscous sound wave damping via magnetostriction for the magnetic case and electrostriction for the polarization case.Comment: 5 pages no figures ReVTeX

Design, processing and testing of LSI arrays, hybrid microelectronics task

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated

Warpage issues in large area mould embedding technologies

The need for higher communications speed, heterogeneous integration and further miniaturisation have increased demand in developing new 3D integrated packaging technologies which include wafer-level moulding and chip-to-wafer interconnections . Wafer-level moulding refers to the embedding of multiple chips or heterogeneous systems on the wafer scale. This can be achieved through a relatively new technology consisting of thermal compression moulding of granular or liquid epoxy moulding compounds. Experimental measurements from compression moulding on 8” blank wafers have shown an unexpected tendency to warp into a cylindrical-shape following cooling from the moulding temperature to room temperature. Wafer warpage occurs primarily as a result of a mismatch between the coefficient of thermal expansion of the resin compound and the Si wafer. This paper will delve into possible causes of such asymmetric warpage related to mould, dimensional and material characteristics using finite element (FE) software (ANSYS Mechanical). The FE model of the resin on wafer deposition will be validated against the measurement results and will be used to deduce appropriate guidelines for low warpage wafer encapsulation.peer-reviewe

Beam lead technology

Beam lead technology for microcircuit interconnections with applications to metallization, passivation, and bondin