20 research outputs found
Towards electromechanical computation: An alternative approach to realize complex logic circuits
Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved. Published by AIP Publishing
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Photonic Interconnection Networks for Applications in Heterogeneous Utility Computing Systems
Growing demands in heterogeneous utility computing systems in future cloud and high performance computing systems are driving the development of processor-hardware accelerator interconnects with greater performance, flexibility, and dynamism. Recent innovations in the field of utility computing have led to an emergence in the use of heterogeneous compute elements. By leveraging the computing advantages of hardware accelerators alongside typical general purpose processors, performance efficiency can be maximized. The network linking these compute nodes is increasingly becoming the bottleneck in these architectures, limiting the hardware accelerators to be restricted to localized computing.
A high-bandwidth, agile interconnect is an imperative enabler for hardware accelerator delocalization in heterogeneous utility computing. A redesign of these systems' interconnect and architecture will be essential to establishing high-bandwidth, low-latency, efficient, and dynamic heterogeneous systems that can meet the challenges of next-generation utility computing.
By leveraging an optics-based approach, this dissertation presents the design and implementation of optically-connected hardware accelerators (OCHA) that exploit the distance-independent energy dissipation and bandwidth density of photonic transceivers, in combination with the flexibility, efficiency and data parallelization offered by optical networks. By replacing the electronic buses with an optical interconnection network, architectures that delocalize hardware accelerators can be created that are otherwise infeasible.
With delocalized optically-connected hardware accelerator nodes accessible by processors at run time, the system can alleviate the network latency issues plague current heterogeneous systems. Accelerators that would otherwise sit idle, waiting for it's master CPU to feed it data, can instead operate at high utilization rates, leading to dramatic improvements in overall system performance.
This work presents a prototype optically-connect hardware accelerator module and custom optical-network-aware, dynamic hardware accelerator allocator that communicate transparently and optically across an optical interconnection network. The hardware accelerators and processor are optimized to enable hardware acceleration across an optical network using fast packet-switching. The versatility of the optical network enables additional performance benefits including optical multicasting to exploit the data parallelism found in many accelerated data sets. The integration of hardware acceleration, heterogeneous computing, and optics constitutes a critical step for both computing and optics.
The massive data parallelism, application dependent-location and function, as well as network latency, and bandwidth limitations facing networks today complement well with the strength of optical communications-based systems. Moreover, ongoing efforts focusing on development of low-cost optical components and subsystems that are suitable for computing environment may benefit from the high-volume heterogeneous computing market. This work, therefore, takes the first steps in merging the areas of hardware acceleration and optics by developing architectures, protocols, and systems to interface with the two technologies and demonstrating areas of potential benefits and areas for future work. Next-generation heterogeneous utility computing systems will indubitably benefit from the use of efficient, flexible and high-performance optically connect hardware acceleration
Design of photonics crystal fiber sensors for bio-medical applications
Photonic Crystal Fibers (PCFs) have special structures and offer a number of novel design options, such as very large or very small mode areas, high numerical aperture, guidance of light in air, and novel dispersion properties.PCFs have become an attractive field for the researchers and they are trying to work on these to get their properties applied in dispersion related applications, sensing applications and much more.PCFs sensors are widely used in bio-medical applications. The sensitivity and performance of sensors are enhanced due to novel applications of PCFs.This paper outlines a novel design for a generalized biomedical sensor by collaborating PCF and electro-optic effect of Lithium Niobate (LiNbO_3) based Mach-Zehnder interferometer (MZI) structure
All Optical Signal Processing Technologies in Optical Fiber Communication
Due to continued growth of internet at starling rate and the introduction of new broadband services, such as cloud computing, IPTV and high-definition media streaming, there is a requirement for flexible bandwidth infrastructure that supports mobility of data at peta-scale. Elastic networking based on gridless spectrum technology is evolving as a favorable solution for the flexible optical networking supportive next generation traffic requirements. Recently, research is centered on a more elastic spectrum provision methodology than the traditional ITU-T grid. The main issue is the requirement for a transmission connect, capable of accommodating and handling a variety of signals with distinct modulation format, baud rate and spectral occupancy. Segmented use of the spectrum could lead to the shortage of availableness of sufficiently extensive spectrum spaces for high bitrate channels, resulting in wavelength contention. On-demand space assignment creates not only deviation from the ideal course but also have spectrum fragmentation, which reduces spectrum resource utilization. This chapter reviewed the recent research development of feasible solutions for the efficient transport of heterogeneous traffic by enhancing the flexibility of the optical layer for performing allocation of network resources as well as implementation of optical node by all optical signal processing in optical fiber communication
Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 115-121).Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade and for technology nodes below 90 nm, the scaling of threshold and supply voltages has slowed, as a result of subthreshold leakage, and power density has increased with each new technology node. This has forced a move toward multi-core architectures, but the energy efficiency benefits of parallelism are limited by the sub-thresahold leakage and the minimum energy point for a given function. Avoiding this roadblock requires an alternative device with more ideal switching characteristics. One promising class of such devices is the electro-statically actuated micro-electro-mechanical (MEM) relay which offers zero leakage current and abrupt turn-on behavior. Although a MEM relay is inherently slower than a CMOS transistor due to the mechanical movement, we have developed circuit design methodologies to mitigate this problem at the system level. This thesis explores such design optimization techniques and investigates the viability of MEM relays as an alternative switching technology for very-large scale integration (VLSI) applications. In the first part of this thesis, the feasibility of MEM relays for power management applications is discussed. Due to their negligibly low leakage, in certain applications, chips utilizing power gates built with MEM relays can achieve lower total energy than those built with CMOS transistors. A simple comparative analysis is presented and provides design guidelines and energy savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. We also demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based pulse generator suitable for self-timed operation. Going beyond power-gating applications, this work also describes circuit techniques and trade-offs for logic design with MEM-relays, focusing on multipliers which are commonly known as the most complex arithmetic units in a digital system. These techniques leverage the large disparity between mechanical and electrical time-constants of a relay, partitioning the logic into large, complex gates to minimize the effect of mechanical delay and improve circuit performance. At the component design level, innovations in compressor unit design minimize the required number of relays for each block and facilitate component cascading with no delay penalty. We analyze the area/energy/delay trade-offs vs. CMOS designs, for typical bit-widths, and show that scaled relays offer 10-20x lower energy per operation for moderate throughputs (<10-100MOPS). In addition to this analysis, we demonstrate the functionality of some of the most complex MEM relay circuits reported to date. Finally, considering the importance of signal generation and transmission in VLSI systems, this thesis presents MEM relay-based I/O units, focusing on design and demonstration of digital to analog converters (DAC). It also explores the concept of faster-than-mechanical-delay signal transmission.by Hossein Fariborzi.Ph.D
Evolution of Transistor Circuits
Der Entwurf von analogen Schaltungen ist ein Bereich der Elektronikentwicklung, der dem Entwickler ein hohes Maß an Wissen und Kreativität beim Lösen von Problemen abverlangt. Bis heute gibt es nur rudimentäre analytische Lösungen um die Bauteile von Schaltungen zu dimensionieren. Motiviert durch diese Herausforderungen, konzentriert sich diese Arbeit auf die automatische Synthese analoger Schaltungen mit Hilfe von Evolutionären Algorithmen. Als analoges Substrat wird ein FPTA benutzt, das ein Feld von konfigurierbaren Transistoren zur Verfügung stellt. Der Einsatz von echter Hardware bietet zwei Vorteile: erstens können entstehende Schaltungen schneller getestet werden als mit einem Simulator und zweitens funktionieren die gefundenen Schaltungen garantiert auf einem echten Chip. Softwareseitig eignen sich Evolutionäre Algorithmen besonders gut für die Synthese analoger Schaltungen, da sie keinerlei Vorwissen über das Optimierungsproblem benötigen. In dieser Arbeit werden neue genetische Operatoren entwickelt, die das Verständnis von auf dem FPTA evolutionierten Schaltungen erleichtern und außerdem Lösungen finden sollen, die auch außerhalb des Substrates funktionieren. Dies ist mit der Hoffnung verbunden, möglicherweise neue und ungewöhnliche Schaltungsprinzipien zu entdecken. Weiterhin wird ein mehrzieliger Optimierungsalgorithmus implementiert und verfeinert, um die Vielzahl von Variablen berücksichtigen zu können, die für die gleichzeitige Optimierung von Topologie und Bauteiledimensionierung notwendig sind. Die vorgeschlagenen genetischen Operatoren, sowie die mehrzielige Optimierung werden für die Evolution von logischen Gattern, Komparatoren, Oszillatoren und Operationsverstärkern eingesetzt. Der Ressourcenverbrauch der durch Evolution gefundenen Schaltungen wird damit vermindert und es ist möglich in einigen Fällen einen übersichtlichen Schaltplan zu erstellen. Ein modulares System für die Evolution von Schaltungen auf konfigurierbaren Substraten wurde entwickelt. Es wird gezeigt, dass mit diesem System FPTA-Architekturen modelliert und direkt für Evolutionsexperimente verwendet werden können
Circuits Techniques for Wireless Sensing Systems in High-Temperature Environments
RÉSUMÉ Dans ce projet, nous proposons de nouvelles techniques d’intégration basées sur la technologie de nitrure de gallium (GaN). Ces techniques permettent de mettre en œuvre un système de transmission de données sans fil entièrement intégré dédié aux capteurs de surveillance pour des applications d'environnement hostile. Le travail nécessite de trouver une technologie capable de résister à l'environnement sévère, principalement à haute température, et de permettre un niveau d'intégration élevé. Le système réalisé serait le premier dispositif de transmission de données basé sur la technologie GaN. En plus de supporter les conditions de haute température (HT) dépassant 600 oC, le système de transmission sans fil attendu devrait fonctionner à travers une barrière métallique séparant le module émetteur du récepteur. Une revue de la littérature sur les applications en environnements hostiles ainsi que sur l'électronique correspondante a été réalisée pour sélectionner la technologie AlGaN/GaN HEMT (transistor à haute mobilité d'électrons) comme une technologie appropriée. Le kit de conception GaN500, fourni par le Conseil national de recherches du Canada (CNRC), a été adopté pour concevoir et mettre en œuvre le système proposé. Cette technologie a été initialement introduite pour desservir les applications radiofréquences (RF) et micro-ondes. Par conséquent, elle n'avait pas été validée pour concevoir et fabriquer des circuits intégrés analogiques et numériques complexes et son utilisation à des températures extrêmes n’était pas validée.
Nous avons donc caractérisé à haute température des dispositifs fabriqués en GaN500 et des éléments passifs intégrés correspondants ont été réalisés. Ces composants ont été testés sur la plage de température comprise entre 25 et 600 oC dans cette thèse. Les résultats de caractérisation ont été utilisés pour extraire les modèles HT des HEMT intégrés et des éléments passifs à utiliser dans les simulations. En outre, plusieurs composants intégrés basés sur la technologie GaN500, notamment des NOT, NOR, NAND, XOR, XNOR, registres, éléments de délais et oscillateurs ont été mis en œuvre et testés en HT. Des circuits analogiques à base de GaN500, comprenant un amplificateur de tension, un comparateur, un redresseur simple alternance, un redresseur double alternance, une pompe de charge et une référence de tension ont également été mis en œuvre et testés en HT.
Le système de transmission de données mis en œuvre se compose d'un module de modulation situé dans la partie émettrice et d'un module de démodulation situé dans la partie réceptrice.----------ABSTRACT
In this project, we propose new integrated-circuit design techniques based on the Gallium Nitride (GaN) technology to implement a fully-integrated data transmission system dedicated to wireless sensing in harsh environment applications. The goal in this thesis is to find a proper technology able to withstand harsh-environments (HEs), mainly characterized by high temperatures, and to allow a high-integration level. The reported design is the first data transmission system based on GaN technology. In addition to high temperature (HT) environment exceeding 600 oC, the expected wireless transmission systems may need to operate through metallic barriers separating the transmitting from the receiving modules.
A wide literature review on the HE applications and corresponding electronics has been done to select the AlGaN/GaN HEMT (high-electron-mobility transistor) technology. The GaN500 design kit, provided by National Research Council of Canada (NRC), was adopted to design and implement the proposed system. This technology was initially provided to serve radio frequency (RF) and microwave circuits and applications. Consequently, it was not validated to implement complex integrated systems and to withstand extreme temperatures. Therefore, the high-temperature characterization of fabricated GaN500 devices and corresponding integrated passive elements was performed over the temperature range 25-600 oC in this thesis. The characterization results were used to extract HT models of the integrated HEMTs and passive elements to be used in simulations. Also, several GaN500-based digital circuits including NOT, NOR, NAND, XOR, XNOR, register, Delay and Ring oscillator were implemented and tested at HT. GaN500-based Analog circuits including front-end amplifier, comparator, half-bridge rectifier, full-bridge rectifier, charge pump and voltage reference were implemented and tested at HT as well. The implemented data transmission system consists of a modulation module located in the transmitting part and a demodulation block located in the receiving part. The proposed modulation system is based on the delta-sigma modulation technique and composed of a front-end amplifier, a comparator, a register, a charge pump and a ring oscillator. The output stage of the transmitter is intended to perform the load-shift-keying (LSK) modulation required to accomplish the data transmission through the dedicated inductive link. At the receiver level, three demodulation topologies were proposed to acquire the delivered LSK-modulated signals
A Common Architecture for Processing Data from Thin Film Sensor Arrays Tailored to 3-D Applications
Thin film sensor arrays on ICs are studied as an example of 3-D integration.
Various thin film sensor arrays are studied, with emphasis on systems integratable
on silicon. 3-D integration offers the chance to have all the data from the sensors
in the sensor arrays available to the processing layer at once. The data from the
sensors is read vertically directly into the processing layer. With the motivation to
identify the needs of various thin film sensors and to exploit the available parallelism
in data, thin film sensors are categorized into two - those with similar sensors in the
arrays or those with different sensors in the sensor array. A common architecture
to address both the categories is proposed, designed and implemented. Such a
generic processing layer design also helps independant development of sensor arrays
(of either categories) and finally deposited on such a generic processing layer.
Also any commercial off the shelf generic microprocessor can not be used for such a project. The reasons being that the generic microprocessors were not designed keeping in mind the vertical integration and hence parallelism in data. Nor are they designed to handle the specific needs of sensor arrays. The modSIMD processor (proposed and implemented in this thesis) exploits the 3-D integration aspects and the needs of sensor arrays. modSIMD stands for a modified SIMD (Single Instruction Multiple Data) architecture. In the common addressing mode, it behaves like a SIMD processor and works on various data elements parallely. In the specific addressing mode, it behaves like a SISD (Single Instruction Single Data) processor.
First the advantages of 3-D integration are studied. The 3-D system architecture is compared to a 2-D system architecture with similar processing architecture. The 3-D architecture is seen to dissipate more power but is more efficient in area and speed. Then the processing architecture is put to test with applications from both the categories. It outperforms an ARM microprocessor in SIMD applications, thus exploiting the parallelism in data. modSIMD also works on applications from both the categories, thus developing such a common architecture is made possible