Effects of cosmic rays on single event upsets

Assistance was provided to the Brookhaven Single Event Upset (SEU) Test Facility. Computer codes were developed for fragmentation and secondary radiation affecting Very Large Scale Integration (VLSI) in space. A computer controlled CV (HP4192) test was developed for Terman analysis. Also developed were high speed parametric tests which are independent of operator judgment and a charge pumping technique for measurement of D(sub it) (E). The X-ray secondary effects, and parametric degradation as a function of dose rate were simulated. The SPICE simulation of static RAMs with various resistor filters was tested

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Advanced Scanning Electron Microscopy Methods and Applications to Integrated Circuit Failure Analysis

Semiconductor device failure analysis using the scanning electron microscope (SEM) has become a standard component of integrated circuit fabrication. Improvements in SEM capabilities and in digital imaging and processing have advanced standard acquisition modes and have promoted new failure analysis methods. The physical basis of various data acquisition modes, both standard and new, and their implementation on a computer controlled SEM image acquisition/processing system are discussed, emphasizing the advantages of each method. Design considerations for an integrated, online failure analysis system are also described. Recent developments in the integration of the information provided by electron beam analysis, conventional integrated circuit (IC) testing, computer-aided design (CAD), and device parameter testing into a single system promise to provide powerful future tools for failure analysis

Above-IC RF MEMS devices for communication applications

Wireless communications are showing an explosive growth in emerging consumer and military applications of radiofrequency (RF), microwave, and millimeter-wave circuits and systems. Applications include wireless personal connectivity (Bluetooth), wireless local area networks (WLAN), mobile communication systems (GSM, GPRS, UMTS, CDMA), satellite communications and automotive electronics. Future cell phones and ground communication systems as well as communication satellites will require more and more sophisticated technologies. The increasing demand for size and weight reduction, cost savings, low power consumption, increased frequency and higher functionality and reconfigurability as part of multiband and multistandard operation is necessitating the use of highly integrated RF front-end circuits. Chip scaling has made a major contribution to this goal, but today a situation has been reached where the presence of numerous off-chip passive RF components imposes a critical bottleneck to further integration and miniaturization of wireless transceivers. Microelectromechanical systems (MEMS) technology is a rapidly emerging enabling technology that is intended to replace the discrete passives by their integrated counterparts. In this thesis, an original metal surface micromachining process, which is compatible with CMOS post-processing, for above-IC integration of RF MEMS tunable capacitors and suspended inductors is presented. A detailed study on SF6 inductively coupled plasma (ICP) releasing has been performed in order to ascertain the optimal process parameters. This study has emphasized the fact that temperature plays an important role in this process by limiting silicon dioxide etching. Moreover, the optimized recipe has been found to be independent of the sacrificial layer used (amorphous or polycrystalline silicon) and its thickness. Using this recipe, 15.6 µm/min Si underetch rate with high Si: SiO2 selectivity (> 20000: 1) has been obtained. Single-air-gap and double-air-gap parallel-plate MEMS tunable capacitors have been designed, fabricated and characterized in the pF range, from 1 MHz to 13.5 GHz. It has been shown that an optimized design of the suspended membrane and direct symmetrical current feed at both ports can significantly improve the quality factor and increase the self-resonant frequency, pushing it to 12 GHz and beyond. The maximum capacitance tuning range obtained for a single-air-gap capacitor is 29% for a bias voltage of 20 V. The maximum capacitance tuning range obtained for a double-air-gap capacitor is 207% for a bias voltage of 70 V. The post-processing of X-FAB BiCMOS wafers has been successfully demonstrated to fabricate monolithically integrated VCOs with above-IC MEMS LC tank. Comparing a suspended inductor and the X-FAB inductor with the same design, it has been shown that increasing the thickness of the spiral from 2.3 to 4 µm and having the spiral suspended 3 µm above the passivation layers lead to an improvement factor of 2 for the peak quality factor and a shift of the self-resonant frequency beyond 15 GHz. No significant variation on bipolar and MOS transistors characteristics due to the post-processing has been observed and we conclude that the variation due to post-processing is in the same range as the wafer-to-wafer variation. Based on our metal surface micromachining process, coplanar waveguide (CPW) MEMS shunt capacitive switches and variable true-time delay lines (V-TTDLs) have been designed, fabricated and characterized in the 1 - 20 GHz range. A novel MEMS device architecture: the SG-MOSFET, which combines a solid-state MOS transistor and a metal suspended gate has been proposed as DC current switch. The corresponding fabrication process using polysilicon as a sacrificial layer has been developed to release metal gate suspended over gate oxide by SF6 plasma. Very abrupt current switches have been demonstrated with subthreshold slope better than 10 mV/decade (better than the theoretical solid-state bulk or SOI MOSFET limit of 60 mV/decade) and ultra-low gate leakage (less than 0.001 pA/µm2) due to the air-gap

Investigation on solid-phase crystallization techniques for low temperature polysilicon thin-film transistors

Low-temperature polysilicon (LTPS) has emerged as a dominant technology for high performance thin-film transistors (TFTs) used in mobile liquid crystal display (LCD) and organic light emitting diode (OLED) display products. As users demand higher quality in flat panel displays with a larger viewing area and finer resolution, the improvement in carrier mobility of LTPS compared to that of hydrogenated amorphous silicon (a-Si:H) makes it an excellent candidate as a channel material for TFT. Advantages include improvements in switching speed and the ability to incorporate peripheral scan and data driver circuitry onto a low cost display substrate. Solid-phase crystallization (SPC) is a useful technique to realize polysilicon films due to its simplicity and low cost compared to excimer-laser annealing (ELA),which has many challenges in back-plane manufacturing on large glass panels.Metal induced crystallization (MIC) results in polycrystalline silicon films with grain size as large as tens of microns. Flash-lamp annealing (FLA) is a new and novel method to crystallize a-Si films at high temperature without distortion of the glass substrate by performing an annealing within millisecond range.This work investigates SPC, MIC and FLA techniques to realize LTPS films. In addition, TFTs were designed and fabricated to characterize the device quality of the semiconductor layer, and to compare the performance of different structural arrangements