The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Síntese de Circuitos Assíncronos com Conflitos: uma Abordagem baseada em Regiões

Doutoramento em Engenharia Electrónica e TelecomunicaçõesCircuitos assíncronos são uma área de investigação presentemente com um largo número de pessoas envolvidas, quer na indústria quer nos meios académicos. Após um longo período de actividade marginal, tópicos como especificação, análise, síntese ou verificação merecem a atenção da comunidade científica. Uma média anual de publicações superior a 100 durante a última década é disso mesmo uma prova. A taxionomia habitual de circuitos assíncronos tem por base o modelo de atraso sob o qual se assume aqueles funcionarem correctamente. A classe dos circuitos assíncronos independentes da velocidade (speed independent asynchronous circuits), que estão na base do trabalho apresentado nesta tese, assumem um atraso das portas lógicas finito mas sem limite superior conhecido e um atraso dos fios de interconexão nulo ou pelo menos desprezável face ao atraso das portas. A especificação nesta classe é normalmente feita usando dois tipos de grafos: grafos de estados, um formalismo tendo por base os estados do circuito, e grafos de transições de sinais, uma classe de redes de Petri onde se descreve as relações de causalidade e concorrência entre os eventos _ transições de sinais _ no circuito. Existem disponíveis ferramentas de síntese automática de circuitos assíncronos independentes da velocidade, merecendo Petrify a nossa especial referência. Dois cenários não são contemplados por estas ferramentas, uma vez que infringem uma condição necessária para a existência de uma solução puramente digital independente da velocidade. Um é caracterizado pela existência de não-persistências envolvendo sinais internos ou de saída, situação típica em árbitros e sincronizadores. Uma metodologia de projecto é apresentada que permite a geração de uma solução recorrendo ao uso de ferramentas de síntese para circuitos independentes da velocidade. Um procedimento de transformação toma, à entrada, uma especificação contendo não-persistências e fornece, à saída, um conjunto de componentes especiais, que lidam com as não-persistências, e uma especificação apropriada para alimentar a ferramenta de síntese. Estabelece-se uma relação entre estados não persistentes e regiões concorrentes, que actuam como secções críticas do sistema. Controlando o acesso a essas regiões, por via da introdução de componentes especiais em hardware, parcialmente analógicos, desempenhando o papel de árbitros, transferem-se os conflitos para os árbitros, ficando o resto do circuito deles isento. Na metodologia proposta, toda a transformação toma a forma de um simples produto de sistemas de transições. Isto resulta da possibilidade de representar os vários passos do procedimento de inserção dos árbitros através de factores multiplicativos. O produto de sistemas de transições goza, se visto em termos de isomorfismo e de grafo alcançável a partir do estado inicial, das propriedades comutativa e associativa, pelo que a ordem de processamento é irrelevante para o resultado final O outro cenário corresponde à existência de não-comutatividades entre eventos de entrada. O problema é analisado e diferentes abordagens para o ultrapassar são apresentadas. Uma das abordagens aponta no sentido da transformação das não-comutatividades em não-persistências, aplicando-se de seguida a metodologia desenvolvida para estas. Uma outra abordagem sugere o controlo das não-comutatividades por via da inserção de dispositivos específicos de arbitragem. A análise apresentada deve ser aprofundada por forma a se definir a metodologia mais apropriada para a resolução deste tipo de conflitos..Asynchronous circuits are a subject of research currently with a large number of people involved, both from academy and industry. After a long period of time of marginal activity, topics like speci_cation, analysis, synthesis, veri_cation have deserve attention of the research community. An average of more then 100 papers per year in the last decade in an evidence of that. The common taxonomy of asynchronous circuits is based on the delay model under which they are assumed to properly operate. The class of speed independent asynchronous circuits, which assumes an unbounded gate delay model, that is, gates have a _nite, no upper limited delay while wires interconnecting gates are assumed to have negligible delays, underlies the work presented in this thesis. Speci_cations are usually described using two types of graph models: state graphs, a state-based formalism, and signal transition graphs, a class of Petri nets. Automatic synthesis tools exist, with Petrify deserving our special attention. Two scenarios in speci_cation are not accepted by these tools, because they infringe a speed independent necessary condition. One is characterized by non-persistences involving non-input signals, which are typical in arbiters and synchronizers. A design methodology is presented that allows the use of existing speed independent tools to derive an implementation for such speci_cations. A transformation procedure takes a speci_cation with non-persistences at input and delivers both a net list of special components managing the non-persistences and a speci_cation suitable to feed the logic synthesis tool. Non-persistences are modeled as exclusion relations among regions, which act like critical sections of the system. Introducing special, partial analog components, acting as arbiters, access to these regions are controlled, transferring the con_ict points to the arbiters and leaving the remainder of the speci_cation free from con_icts. In the proposed methodology the overall transformation takes the simple form of products of transition systems. In the region-based model used, the several steps for the insertion of an arbiter into the speci_cation can be represented as transition system factors. Thus the product form can be achieved. Up to reachability and isomorphism, the product of transition systems holds the commutative and associative properties. The order of processing of di_erent non-persistences is thus irrelevant to the _nal result. The other scenario corresponds to the existence of non-commutativities between input events. The problem is analyzed and di_erent approaches to solve it are discussed. One approach suggests the transformation of the non-commutativities into nonpersistences, allowing for the subsequent application of the methodology developed for non-persistences. Another approach suggests the control of non-commutativities by means of the insertion of speci_c arbitration entities. Non-commutativities must however be further analyzed in order to de_ne and develop a proper methodology to solve this kind of con_icts

Proceedings of the Caltech Conference on Very Large Scale Integration, held at the California Institute of Technology 22 - 24 January 1979 ; Organized by the Caltech Computer Science Department and the Caltech Industrial Associates Office

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Optimisation of the bolometric performances of the CUORE-0/CUORE and LUCIFER detectors for the neutrinoless double beta decay search.

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Recent Advances in Multi Robot Systems

To design a team of robots which is able to perform given tasks is a great concern of many members of robotics community. There are many problems left to be solved in order to have the fully functional robot team. Robotics community is trying hard to solve such problems (navigation, task allocation, communication, adaptation, control, ...). This book represents the contributions of the top researchers in this field and will serve as a valuable tool for professionals in this interdisciplinary field. It is focused on the challenging issues of team architectures, vehicle learning and adaptation, heterogeneous group control and cooperation, task selection, dynamic autonomy, mixed initiative, and human and robot team interaction. The book consists of 16 chapters introducing both basic research and advanced developments. Topics covered include kinematics, dynamic analysis, accuracy, optimization design, modelling, simulation and control of multi robot systems

A Beam Interlock System for CERN High Energy Accelerators

The Large Hadron Collider (LHC) at CERN (The European Organisation for Nuclear Research) is one of the largest and most complicated machines envisaged to date. The LHC has been conceived and designed over the course of the last 25 years and represents the cutting edge of accelerator technology with a collision energy of 14TeV, having a stored beam energy over 100 times more powerful than the nearest competitor. Commissioning of the machine is already nderway and operation with beam is intended for Autumn 2007, with 7TeV operation expected in 2008. The LHC is set to answer some of the fundemental questions in theoretical physics, colliding particles with such high energy that the inner workings of the quantum world can be revealed. Colliding particles together at such high energy makes very high demands on machine operation and protection. The specified beam energy requires strong magnetic fields that are made in superconducting dipole magnets, these magnets are kept only around two degrees above absolute zero and there is a high chance of particle impacts causing a magnet to quench, where the magnet becomes normal conducting and has to be switched off before it destroys itself. Losing as little as 10eâ8 of the beam into the superconducting magnets will lead to a quench. A loss of 10eâ4 of the beam into any part of the machine will cause damage, such as rupturing the machine vacuum, which in the best case results in costly repairs and weeks of downtime, in a worse case the destruction of one or more dipole magnets would mean many weeks of repairs to return the machine to operation. Due to the unprecedented sensitivity of the machine to beam losses, and the high cost of failure, both financially and in terms of inefficiency, a complex Machine Protection System is envisaged, surveilling and diagnosing the operation of the CERN high energy accelerators, ensuring their safe operation. Machine Protection Systems are employed in the LHC, SPS and beam transfer lines, protecting all parts of the accelerator complex that handle beam above damage thresholds. At the heart of each Machine Protection System lies a Beam Interlock System, connecting the many components of the Machine Protection Systems which are located all around the accelerator complex. The LHC is the ultimate application of these protection systems, here the Beam Interlock System is responsible for relaying a command for controlled removal of the beam (Beam Dump) to the LHC Beam Dumping System. The Beam Dumping System is the only part of the accelerator that is capable of withstanding the impact of the full LHC beam without being damaged in the process. The time response of the LHC Beam nterlock System has to be around 100$/mu$s, to protect against the fastest events which lead to beam losses. Each Beam Interlock System is made from sixteen Beam Interlock Controllers. These are distributed around the 27km circumference of the machine, one at the left and one at the right of each Insertion Region, each Controller acts as a local concentrator, monitoring up to 14 User System inputs. Fibre optic links join the sixteen Controllers in so-called beam permit loops, making the high-speed, highly dependable backbone of the Beam Interlock System. This thesis is focussed on the conception, design and realisation of a generic Beam Interlock System used to protect the high energy accelerators at CERN. The Beam Interlock System has been designed to provide the LHC and its injector chain, as well as the SPS and its transfer lines, including the CERN Neutrinos to Gran Sasso project, with an unsurpassed level of protection. In every application the stored beam energy is orders of magnitude above the damage thresholds of the machines

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumption and high energy efficiency have emerged as the two key criteria for embedded microprocessor design. In this thesis we present a range of microarchitectural low-power design techniques which enable the increase of performance for embedded microprocessors and/or the reduction of energy consumption, e.g., through voltage scaling. In the context of cryptographic applications, we explore the effectiveness of instruction set extensions (ISEs) for a range of different cryptographic hash functions (SHA-3 candidates) on a 16-bit microcontroller architecture (PIC24). Specifically, we demonstrate the effectiveness of light-weight ISEs based on lookup table integration and microcoded instructions using finite state machines for operand and address generation. On-node processing in autonomous wireless sensor node devices requires deeply embedded cores with extremely low power consumption. To address this need, we present TamaRISC, a custom-designed ISA with a corresponding ultra-low-power microarchitecture implementation. The TamaRISC architecture is employed in conjunction with an ISE and standard cell memories to design a sub-threshold capable processor system targeted at compressed sensing applications. We furthermore employ TamaRISC in a hybrid SIMD/MIMD multi-core architecture targeted at moderate to high processing requirements (> 1 MOPS). A range of different microarchitectural techniques for efficient memory organization are presented. Specifically, we introduce a configurable data memory mapping technique for private and shared access, as well as instruction broadcast together with synchronized code execution based on checkpointing. We then study an inherent suboptimality due to the worst-case design principle in synchronous circuits, and introduce the concept of dynamic timing margins. We show that dynamic timing margins exist in microprocessor circuits, and that these margins are to a large extent state-dependent and that they are correlated to the sequences of instruction types which are executed within the processor pipeline. To perform this analysis we propose a circuit/processor characterization flow and tool called dynamic timing analysis. Moreover, this flow is employed in order to devise a high-level instruction set simulation environment for impact-evaluation of timing errors on application performance. The presented approach improves the state of the art significantly in terms of simulation accuracy through the use of statistical fault injection. The dynamic timing margins in microprocessors are then systematically exploited for throughput improvements or energy reductions via our proposed instruction-based dynamic clock adjustment (DCA) technique. To this end, we introduce a 6-stage 32-bit microprocessor with cycle-by-cycle DCA. Besides a comprehensive design flow and simulation environment for evaluation of the DCA approach, we additionally present a silicon prototype of a DCA-enabled OpenRISC microarchitecture fabricated in 28 nm FD-SOI CMOS. The test chip includes a suitable clock generation unit which allows for cycle-by-cycle DCA over a wide range with fine granularity at frequencies exceeding 1 GHz. Measurement results of speedups and power reductions are provided