731 research outputs found

    Mechanocapillary Forming of Filamentary Materials.

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    The hierarchical structure and organization of filaments within natural materials determine their collective chemical and physical functionalities. Synthetic nanoscale filaments such as carbon nanotubes (CNTs) are known for their outstanding properties including high stiffness and strength at low density, and high electrical conductivity and current carrying capacity. Ordered assemblies of densely packed CNTs are therefore expected to enable the synthesis of new materials having outstanding multifunctional performance. However, current methods of CNT synthesis have inadequate control of quality, density and order. In pursuit of these needs, a new technique called capillary forming is used to manipulate vertically aligned (VA-) CNTs, and to enable their integration in applications ranging from microsystems to macroscale functional films. Capillary forming relies on shape-directed capillary rise during solvent condensation; followed by evaporation-induced shrinkage. Three-dimensional geometric transformations result from the heterogeneous strain distribution within the microstructures during the vapor-liquid-solid interface shrinkage. A portfolio of microscale CNT assemblies with highly ordered internal structure and freeform geometries including straight, bent, folded and helical profiles, are fabricated using this technique. The mechanical stiffness and electrical conductivity of capillary formed CNT micropillars are 5 GPa and 104 S/m respectively. These values are at least hundred-fold higher than as-grown CNT properties, and exceed the properties of typical microfabrication polymers. Responsive CNT-hydrogel composites are prototyped by combining isotropic moisture-induced swelling of the hydrogel with the anisotropic stiffness of CNTs to induce reversible self-directed shape changes of up to 30% stroke. Centimeter scale sheets are fabricated by mechanical rolling and capillary assisted joining of CNTs. The mechanical stiffness, strength and electrical conductivity of CNT sheets are comparable to those of continuous CNT microstructures; and can be tuned by engineering the morphology of the CNT joints. Finally, the applicability of mechanocapillary forming to other nanoscale filaments is demonstrated using silicon nanowires synthesized by metal assisted chemical etching. Further work using the methods developed in this dissertation could enable applications such as directional liquid transport, adhesives, and biosensors; toward an end goal of creating multifunctional surfaces having arbitrary structural, interfacial, and optical responsiveness.Ph.D.Mechanical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91466/1/stawfick_1.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/91466/2/stawfick_2.pd

    Developing germanium on nothing (GON) nanowire arrays

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    Advanced crystal growth techniques enable novel devices and circuit designs to further scale and integrate heterogeneous structures for CMOS, MEMS/NEMS, and optoelectronic applications. In particular, nanowires (NW) are among the promising structures derived from these developments. Research has demonstrated the utility of NWs as a channel material for gate-all-around transistors, high sensitivity biological/chemical sensors, photodetectors, as well as a whole spectrum of LEDs and lasers. However, NW based devices are not without their fabrication challenges. Relatively simple structures for CMOS or MEMS/NEMS processes are difficult to reproduce when many NW based devices rely on a dropcast process. This thesis demonstrates a method for producing Germanium on Nothing (GON) NW arrays on a Si substrate that forgoes dropcasting and, instead, creates NWs via selective material removal methods commonly utilized by industry. GON NW arrays are formed through the sequential use of E-beam lithography, selective wet chemical etching, and reactive ion etching. Global oxide thinning in BOE leaves a thin masking layer that protects the underlying Si, preventing etching in a TMAH solution. GON regions are defined by E-beam lithography and are subject to a RIE which creates release points in the remaining SiO2. Unmasked Si is then etched by a TMAH solution, undercutting the Ge lines, leaving an array of suspended Ge wires. NW dimensions are reached by thinning the Ge wire diameter with a H2O2 solution. NWs with ~50 nm diameters and ~ 200 nm lengths, as well as 10 [micron] by 10 [micron] membranes of Ge/SiO2, have been demonstrated in this thesis

    Suspended 1D metal oxide nanostructure-based gas sensor

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    Department of Materials Science and EngineeringWe developed a novel batch fabrication technology for the ultralow-power-consumption metal oxide gas sensing platform consisting of a suspended glassy carbon heating nanostructure and hierarchical metal oxide nanostructures forests fabricated by the carbon-micro electromechanical systems (carbon-MEMS) and selective nanowire growth process. We have developed a new manufacturing process for suspended glass carbon nanostructures such as single nanowire, nano-mesh and nano-membranes fabricated using carbon-MEMS consisting of the UV-lithography and the polymer pyrolysis processes. We designed a gas sensing platform consisting of suspended glassy carbon heating nanostructures and suspended hierarchical metal oxide nanostructure forests for the sensing part. Glassy carbon structure produced by the carbon-MEMS has many advantages such as high thermal & chemical stabilities, good hardness, and good thermal & electrical characteristics. The electrical conductivity of glassy carbon nanostructures has been increased more than three times by using rapid thermal annealing (RTA) process owing to the inferior heating property of glassy carbon nano-heater in the electrical conductivity. In order to divide the suspended glassy carbon nano-heater and the suspended hierarchical metal oxide nanostructures forests, the insulating layer of HfO2 materials is a high dielectric constant and is deposited uniformly using a atomic layer deposition (ALD) process on a suspended glassy carbon nano-heater. Suspended hierarchical metal oxide nanostructures forests were grown circumferentially on the suspended HfO2/glassy carbon nano-heater using a hydrothermal method consisting of the seed deposition and the growth processes. For selective metal oxide seed layer deposition process, a short-time exposed polymer patterning process was performed using the positive photoresist. After the polymer patterning process, a metal oxide seed layer is deposited using the rf-sputtering system, followed by a metal oxide nanostructure growth process. The distinguishing architecture of a suspended hierarchical metal oxide nanostructures forests/HfO2/glassy carbon nanostructure ensures efficient mass transport to the metal oxide nanostructure detection point of the gas analyte, resulting in highly sensitive gas detection. In the absence of an external heating system, the ultralow-power-consumption gas sensing platform of a suspended hierarchical metal oxide nanostructures forests/HfO2/glassy carbon nanostructure has excellent the gas sensing characteristics.ope

    III-V์กฑ ํ™”ํ•ฉ๋ฌผ ๋ฐ˜๋„์ฒด ํ„ฐ๋„ ์ „๊ณ„ ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ ๊ฐœ๋ฐœ

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2022. 8. ์ตœ์šฐ์˜.๋ฆฌ์†Œ๊ทธ๋ž˜ํ”ผ ๊ธฐ์ˆ ์˜ ๋†€๋ผ์šด ๋ฐœ์ „์€ 10 nm ์ดํ•˜์˜ ๋…ผ๋ฆฌ ํŠธ๋žœ์ง€์Šคํ„ฐ๋ฅผ ์ƒ์šฉํ™”ํ–ˆ๋‹ค. ๊ฒŒ์ดํŠธ ๊ธธ์ด ์Šค์ผ€์ผ๋ง์€ ๋ชจ์ŠคํŽซ (MOSFET)์˜ ์ „๋ ฅ ์†Œ๋น„๋ฅผ ์ค„์ด๊ธฐ ์œ„ํ•œ ๋…ธ๋ ฅ์˜ ํฐ ๋ถ€๋ถ„์„ ์ฐจ์ง€ํ•œ๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ์ด๋Ÿฌํ•œ ์ ‘๊ทผ ๋ฐฉ์‹์€ ๋ฆฌ์†Œ๊ทธ๋ž˜ํ”ผ์˜ ๋ฌผ๋ฆฌ์  ํ•œ๊ณ„์™€ ๋ˆ„์„ค ์ „๋ฅ˜ ์ œ์–ด์™€ ๊ฐ™์€ ๋ช‡ ๊ฐ€์ง€ ๋ฌธ์ œ์— ์ง๋ฉดํ–ˆ๋‹ค. ๋ชจ์ŠคํŽซ์˜ ๊ทผ๋ณธ์ ์ธ ๋ฌธ์ œ๋Š” ํ˜„์žฌ ์ „์†ก ๋ฉ”์ปค๋‹ˆ์ฆ˜์˜ ํ•œ๊ณ„๋กœ ์ธํ•ด 60 mV/dec ๋ฏธ๋งŒ์˜ ์ž„๊ณ„๊ฐ’ ๊ธฐ์šธ๊ธฐ (SS)์— ๋„๋‹ฌํ•  ์ˆ˜ ์—†๋‹ค๋Š” ๊ฒƒ์ด๋‹ค. Si ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ (TFET)์˜ ์—ฌ๋Ÿฌ ์—ฐ๊ตฌ์ž๋“ค์ด 60 mV/dec ๋ฏธ๋งŒ์˜ ๊ฒฐ๊ณผ๋ฅผ ๋ณด๊ณ ํ–ˆ์ง€๋งŒ, Si ๋™์ข… ์ ‘ํ•ฉ ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ๋Š” ๊ฐ„์ ‘ ๋Œ€์—ญ ๊ฐญ ๋ฌผ์งˆ์˜ ํ„ฐ๋„๋ง ํ™•๋ฅ ์ด ๋‚ฎ์•„ ์ „๋ฅ˜์ƒ์œผ๋กœ ๋ถˆ์ถฉ๋ถ„ํ•˜๋‹ค. P-I ์ ‘ํ•ฉ๋ถ€์—์„œ์˜ ํ„ฐ๋„๋ง ํ™•๋ฅ ์€ ํ„ฐ๋„๋ง ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ์˜ ๋™์ž‘์ „๋ฅ˜์— ์˜ํ–ฅ์„ ๋ฏธ์น˜๊ธฐ ๋•Œ๋ฌธ์— ์ž‘์€ ์ง์ ‘ ๋ฐด๋“œ๊ฐญ์„ ๊ฐ€์ง€๊ณ  ์œ ํšจ์งˆ๋Ÿ‰์ด ๋‚ฎ์€ III-V ํ™”ํ•ฉ๋ฌผ ๋ฐ˜๋„์ฒด๋Š” ์ž„๊ณ„๊ฐ’ ๊ธฐ์šธ๊ธฐ๊ฐ€ 60 mV/dec ๋ฏธ๋งŒ์ธ ๋†’์€ ํ„ฐ๋„๋ง ์ „๋ฅ˜๋ฅผ ๋‹ฌ์„ฑํ•  ์ˆ˜ ์žˆ๋Š” ๊ฐ€์žฅ ์œ ๋งํ•œ ์žฌ๋ฃŒ์ด๋‹ค. ๋˜ํ•œ ๋ฐด๋“œ ์˜คํ”„์…‹์ด ๋‹ค๋ฅธ ์žฌ๋ฃŒ๋ฅผ ์„ ํƒํ•จ์œผ๋กœ์จ, ์Šคํƒœ๊ฑฐ๋“œ ๋˜๋Š” ๋ธŒ๋กœํฐ ๊ฐญ์„ ํ˜•์„ฑํ•จ์œผ๋กœ์จ ํ„ฐ๋„๋ง ์ „๋ฅ˜๋ฅผ ํ˜„์ €ํ•˜๊ฒŒ ์ฆ๊ฐ€์‹œํ‚ฌ ์ˆ˜ ์žˆ๋‹ค. P-I ์ ‘ํ•ฉ๋ถ€์˜ ํ„ฐ๋„๋ง์ด ํ„ฐ๋„ ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ ์†Œ์ž์˜ ์ „๋ฅ˜ ๊ณต๊ธ‰์›์ด๊ธฐ ๋•Œ๋ฌธ์— ๋งŽ์€ ์—ฐ๊ตฌ์ž๋“ค์ด ๋ถ„์ž๋น” ์—ํ”ผํƒ์‹œ (MBE) ๋ฐฉ์‹์œผ๋กœ ์„ฑ์žฅํ•œ pํ˜• ๋„ํ•‘ ๋†๋„๊ฐ€ ๋†’์€ III-V ์›จ์ดํผ๋กœ ์ œ์กฐ๋œ ํ„ฐ๋„ ์ „๊ณ„ํšจ๊ณผ ํŠธ๋žœ์ง€์Šคํ„ฐ์˜ ์„ฑ๋Šฅ์„ ๋ณด๊ณ ํ•ด์™”๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ๋†’์€ ๋„ํ•‘ ๋†๋„์™€ ๊ฐ€ํŒŒ๋ฅธ ๋„ํŽ€ํŠธ ํ”„๋กœํŒŒ์ผ์„ ๊ฐ–๋Š” pํ˜• InGaAs๋ฅผ ์„ฑ์žฅํ•˜๊ธฐ๊ฐ€ ๊นŒ๋‹ค๋กญ๊ธฐ ๋•Œ๋ฌธ์— ๊ธˆ์†-์œ ๊ธฐ ํ™”ํ•™ ๊ธฐ์ƒ ์ฆ์ฐฉ (MOCVD) ์„ฑ์žฅ ์—ํ”ผํƒ์…œ ์ธต์—์„œ ์ œ์กฐ๋œ InGaAs TFET ์†Œ์ž๋Š” ๊ฑฐ์˜ ๋ณด๊ณ ๋˜์ง€ ์•Š์•˜๋‹ค. ์ด์— ๋”ฐ๋ผ ๋ณธ ์—ฐ๊ตฌ๋Š” TFET ์†Œ์ž ์ œ์ž‘์„ ์œ„ํ•œ ๊ณ ํ’ˆ์งˆ ์—ํ”ผํƒ์…œ ์ธต์„ ์„ฑ์žฅ์‹œํ‚ค๊ธฐ ์œ„ํ•œ MOCVD ์„ฑ์žฅ ๊ธฐ์ˆ ์„ ์„ ๋ณด์ธ๋‹ค. ์ข…๋ž˜์˜ TFET ์†Œ์ž์— ๋Œ€ํ•ด์„œ๋Š” ๋™์ข… ์ ‘ํ•ฉ p-i-n InGaAs ์—ํ”ผํƒ์…œ์ธต์„ ์„ฑ์žฅ์‹œํ‚ค๊ณ , p++-Ge/i-InGaAs/n+-InAs ๋‚˜๋…ธ์„ ์„ ์„ฑ์žฅ์‹œ์ผœ TFET ์†Œ์ž ์„ฑ๋Šฅ ํ–ฅ์ƒ ๊ฐ€๋Šฅ์„ฑ์„ ํ™•์ธํ•˜์˜€๋‹ค. MOCVD์— ์˜ํ•ด ์„ฑ์žฅํ•œ ์—ํ”ผํƒ์‹œ ์ธต์—์„œ ์ œ์กฐ๋œ TFET ์†Œ์ž์˜ ์ž ์žฌ์„ฑ์„ ํ™•์ธํ•˜๊ธฐ ์œ„ํ•ด ํ‰ํŒ๊ณผ ๋‚˜๋…ธ์„  ์—ํ”ผํƒ์…œ ์ธต์—์„œ ์ œ์ž‘๋œ TFET ์†Œ์ž์˜ ์„ฑ๋Šฅ์ด ํ™•์ธ๋˜์—ˆ๋‹ค. MOCVD ๋ฐฉ๋ฒ•์„ ์ด์šฉํ•˜์—ฌ ๊ณ ํ’ˆ์งˆ์˜ ์—ํ”ผํƒ์…œ ์ธต์ด ์„ฑ์žฅ๋˜์—ˆ๋‹ค. MBE์— ๋น„ํ•ด ๊ฐ€์„ฑ๋น„, ๋†’์€ ์ฒ˜๋ฆฌ๋Ÿ‰, ์šฐ์ˆ˜ํ•œ ๊ฒฐ์ • ํ’ˆ์งˆ์ด MOCVD์˜ ๊ฐ€์žฅ ํฐ ์žฅ์ ์ด๋‹ค. ์ด์— ์—ฌ๋Ÿฌ ์„ฑ์žฅ ์กฐ๊ฑด์„ ๋ณ€ํ™”์‹œํ‚ค๋ฉด์„œ InP (001) ๊ธฐํŒ ์œ„๋กœ InGaAs ํ•„๋ฆ„์ธต์˜ ์„ฑ์žฅ์ด ์—ฐ๊ตฌ๋˜์—ˆ๋‹ค. ์†Œ์Šค ์œ ๋Ÿ‰, ์˜จ๋„ ๋ฐ V/III ๋น„์œจ์ด ์„ฑ์žฅ๋œ InGaAs ํ•„๋ฆ„์ธต์˜ ํ’ˆ์งˆ์— ๋ผ์น˜๋Š” ์˜ํ–ฅ์ด ์—ฐ๊ตฌ๋˜์—ˆ๋‹ค. ๋˜ํ•œ MOCVD InGaAs ์„ฑ์žฅ ๊ธฐ์ˆ ์—์„œ nํ˜• ๋ฐ pํ˜• ๋„ํŽ€ํŠธ์˜ ๋†๋„๋ฅผ ๋†’์ด๋Š” ๊ฒƒ๊ณผ ๋„ํŽ€ํŠธ ํ”„๋กœํŒŒ์ผ์„ ๊ฐ€ํŒŒ๋ฅด๊ฒŒ ํ•˜๋Š” ๊ฒƒ์ด ๋„์ „์ ์ด๋ฏ€๋กœ ํƒ„์†Œ ๋ฐ ํ…”๋ฃจ๋ฅจ ๋„ํ•‘์„ ํ†ตํ•ด ๊ฐ€ํŒŒ๋ฅธ ๋„ํŽ€ํŠธ ํ”„๋กœํŒŒ์ผ์„ ๋ณด์ด๋Š” ๊ณ ๋†๋„์˜ pํ˜• ๋ฐ nํ˜• InGaAs์ธต์„ ์„ฑ์žฅํ•˜์˜€๋‹ค. ์„ฑ์žฅ๋œ ์—ํ”ผํƒ์…œ ํ•„๋ฆ„์ธต์€ TFET ์†Œ์ž๋ฅผ ์ œ์ž‘ํ•˜์—ฌ ํ‰๊ฐ€ํ•˜์˜€๋‹ค. TFET ์†Œ์ž ์ œ์ž‘ ์ „์— ์šฐ์„  TFET ์†Œ์ž์˜ ์ฑ„๋„ ๊ธธ์ด๊ฐ€ ์ „๊ธฐ์  ์‹œ๋ฎฌ๋ ˆ์ด์…˜ ๊ฒฐ๊ณผ์— ์˜ํ•ด ์„ ํƒ๋˜์—ˆ๋‹ค. MOCVD๋ฅผ ์ด์šฉํ•˜์—ฌ ๋„ํ•‘ ํ”„๋กœํŒŒ์ผ์ด ๊ฐ€ํŒŒ๋ฅธ ๊ณ ํ’ˆ์งˆ์˜ ์ˆ˜์ง p-i-n ์—ํ”ผํ…์…œ ๊ตฌ์กฐ๊ฐ€ ํ•œ๋ฒˆ์— ์„ฑ์žฅ๋˜์—ˆ๋‹ค. ์—ํ”ผํƒ์…œ ์„ฑ์žฅ ํ›„์— TFET ์†Œ์ž๋Š” ์ˆ˜์ง ๋ฐฉํ–ฅ์˜ ์Šต์‹ ์‹๊ฐ์„ ํ†ตํ•ด ์ œ์ž‘๋˜์—ˆ๋‹ค. ์˜ด (Ohmic) ๊ณต์ •๊ณผ ์—์–ด๋ธŒ๋ฆฟ์ง€ ๊ณต์ •๋„ ์†Œ์ž ์ œ์ž‘์„ ์œ„ํ•ด ์ตœ์ ํ™”๋˜์—ˆ๋‹ค. Pํ˜• ๋„ํ•‘ ๋†๋„์— ๋Œ€ํ•œ ์˜ํ–ฅ๊ณผ MOCVD ์„ฑ์žฅ ์ค‘์— ์ƒ๊ธด ์ „์œ„์— ๋Œ€ํ•œ ์˜ํ–ฅ์ด TFET ์„ฑ๋Šฅ์„ ํ†ตํ•˜์—ฌ ํ™•์ธ๋˜์—ˆ๋‹ค. ์ œ์กฐ๋œ TFET ์†Œ์ž๋Š” 60 mV/dec์— ๊ฐ€๊นŒ์šด SS์™€ ๊ดœ์ฐฎ์€ ์˜จ/์˜คํ”„ ์ „๋ฅ˜ ๋น„์œจ์„ ๋ณด์—ฌ์ฃผ์—ˆ๋Š”๋ฐ, ์ด๋Š” ์ตœ์ดˆ๋กœ ๋ณด๊ณ ๋˜๋Š” MBE์—์„œ ์„ฑ์žฅ๋œ ์›จ์ดํผ์—์„œ ๋งŒ๋“ค์–ด์ง„ TFET ์†Œ์ž์™€ ๋น„๊ตํ•  ์ˆ˜ ์žˆ๋Š” ์†Œ์ž์ด๋‹ค. ์ด ๊ฒฐ๊ณผ๋Š” ๊ณ ํ’ˆ์งˆ์˜ MOCVD๋กœ ์„ฑ์žฅํ•œ III-V TFET ์†Œ์ž์˜ ์–‘์‚ฐ ๊ฐ€๋Šฅ์„ฑ์„ ๋ณด์—ฌ์ค€๋‹ค. ์ด ์—ฐ๊ตฌ์˜ ๋‹ค์Œ ๋ถ€๋ถ„์€ ๋‚˜๋…ธ์„  TFET ์ œ์ž‘์ด๋‹ค. ์ „์ž์†Œ์ž ์ œ์ž‘์„ ์œ„ํ•œ III-V ๋‚˜๋…ธ์„  ์„ฑ์žฅ์—๋Š” ๋ช‡ ๊ฐ€์ง€ ์žฅ์ ์ด ์žˆ๋‹ค. ๋‹ค์–‘ํ•œ ์ข…๋ฅ˜์˜ ์›จ์ดํผ์— ๋‹ค์–‘ํ•œ ํŠน์„ฑ์„ ๊ฐ€์ง€๋Š” ํ—คํ…Œ๋กœ ๊ตฌ์กฐ๋ฅผ ํ˜•์„ฑํ•  ์ˆ˜ ์žˆ๋‹ค๋Š” ๊ฒƒ์ด ํฐ ์žฅ์ ์ด๋‹ค. ์ถฉ๋ถ„ํžˆ ์ž‘์€ ์ง๊ฒฝ์œผ๋กœ ์„ฑ์žฅ๋œ ๋‚˜๋…ธ์„ ์€ ์›จ์ดํผ์™€ ๋‹ค๋ฅธ ๊ฒฉ์ž ์ƒ์ˆ˜๋ฅผ ๊ฐ€์ง€๋”๋ผ๋„ ์ „์œ„ ์—†๋Š” ๊ณ„๋ฉด์„ ๊ฐ€์ง„๋‹ค. ๋‹ค์–‘ํ•œ ์œ ํ˜•์˜ ๋ฐด๋“œ ์ •๋ ฌ์ด ๋งŒ๋“ค์–ด์งˆ ์ˆ˜ ์žˆ์œผ๋ฉฐ, ์ด๋Š” TFET์˜ ํ„ฐ๋„๋ง ์ •๋ฅ˜๋ฅผ ์ฆ๊ฐ€์‹œํ‚ค๋Š” ๋ฐ์— ์žˆ์–ด ์ค‘์š”ํ•œ ์š”์†Œ์ด๋‹ค. ๋˜ํ•œ ์ง๊ฒฝ์ด ์ž‘์€ ๋‚˜๋…ธ์„ ์€ ์นฉ์œผ๋กœ ์ œ์ž‘๋˜์—ˆ์„ ๋•Œ ๋” ๋‚˜์€ ์†Œ์ž ๋ฐ€๋„, ํ–ฅ์ƒ๋œ ๊ฒŒ์ดํŠธ ์ œ์–ด์„ฑ, ์„ฑ์žฅ ์‹œ๊ฐ„ ๋‹จ์ถ•์„ ํ†ตํ•œ ์ฒ˜๋ฆฌ๋Ÿ‰ ํ–ฅ์ƒ์ด ๊ฐ€๋Šฅํ•˜๋‹ค. InGaAs ๋‚˜๋…ธ์„ ์€ ์„ ํƒ์  ์˜์—ญ ์„ฑ์žฅ๋ฒ• (SAG) ์„ฑ์žฅ๋˜์—ˆ๋‹ค. ํ•˜๋“œ๋งˆ์Šคํฌ ์ธต์œผ๋กœ์„œ InP (111)B ๋ฐ Ge (111) ์›จ์ดํผ์— SiO2 ์ธต์ด ์ฆ์ฐฉ ๋˜์—ˆ๋‹ค. ์„ฑ์žฅ ๋ชจ๋“œ๊ฐ€ ๋‹ค๋ฅด๊ธฐ ๋•Œ๋ฌธ์— InGaAs ํ‰ํŒ ํ•„๋ฆ„์ธต ์„ฑ์žฅ๊ณผ๋Š” ํฌ๊ฒŒ ๋‹ค๋ฅธ ์„ฑ์žฅ ์กฐ๊ฑด์„ ํ…Œ์ŠคํŠธํ•˜์˜€๋‹ค. ๋‚˜๋…ธ์„ ์˜ ์„ ํƒ์  ์„ฑ์žฅ์€ ์˜จ๋„, V/III ๋น„์œจ ๋ฐ ์†Œ์Šค ์œ ๋Ÿ‰์„ ์ตœ์ ํ™”ํ•˜์—ฌ ํ™•์ธํ•˜์˜€๋‹ค. ๊ทธ ๊ฒฐ๊ณผ InP (111)B์™€ Ge (111) ์›จ์ดํผ์—์„œ InAs์™€ InGaAs ๋‚˜๋…ธ์„ ์„ ์„ฑ๊ณต์ ์œผ๋กœ ์„ฑ์žฅ์‹œ์ผฐ๋‹ค. Pํ˜• ๋ฌผ์งˆ๋กœ๋Š” p++๋„ํ•‘๋œ Ge (111) ์›จ์ดํผ๋ฅผ ์‚ฌ์šฉํ•˜์˜€๋‹ค. ์ธํŠธ๋ฆฐ์‹ InGaAs์™€ InAs ๋‚˜๋…ธ์„ ์ด ๊ทธ ์œ„์— ์„ ํƒ์ ์œผ๋กœ ์„ฑ์žฅ๋˜์—ˆ๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ ์‹ค๋ฆฌ์ฝ˜ ๋„ํŽ€ํŠธ๋ฅผ ๊ฐ€์ง„ nํ˜• InAs ๋‚˜๋…ธ์„ ์ด ํ›„์†์ ์œผ๋กœ ์„ฑ์žฅ๋˜์—ˆ๋‹ค. ์„ฑ์žฅ๋œ ๋‚˜๋…ธ์„ ์€ ์ˆ˜์ง ๋‚˜๋…ธ์„  TFET์„ ์ œ์ž‘ํ•˜์—ฌ ํ‰๊ฐ€๋˜์—ˆ๋‹ค. ๋†’์€ ๋‹จ๊ณ„ ์ปค๋ฒ„๋ฆฌ์ง€์™€ ์–‘ํ˜ธํ•œ ์ธํ„ฐํŽ˜์ด์Šค ์ƒํƒœ ๋ฐ€๋„๋ฅผ ์œ„ํ•˜์—ฌ ALD HfO2 ๋ฐ ALD TiN ๊ณต์ •๊ณผ์ •์ด ์ตœ์ ํ™”๋˜์—ˆ๋‹ค. ๊ฐœ๋ฐœ๋œ ALD ๊ณต์ •์„ ์ ์šฉํ•จ์œผ๋กœ์จ ์ˆ˜์งํ˜• ๋‚˜๋…ธ์„  Ge/InGaAs ํ—คํ…Œ๋กœ ์ ‘ํ•ฉ TFET์˜ ๋™์ž‘์ด ์„ฑ๊ณต์ ์œผ๋กœ ํ™•์ธ๋˜์—ˆ๋‹ค.The remarkable development of lithography technology commercialized the sub-10 nm logic transistors. Gate length scaling is a large portion of the effort to reduce the power consumption of metal-oxide-semiconductor field-effect transistors (MOSFETs). However, this approach faces several problems, such as the physical limitation of lithography and leakage current control. The fundamental problem of MOSFETs is that they cannot reach subthreshold-slope (SS) below 60 mV/dec due to their current transport mechanism. Several researchers of Si tunneling field-effect transistors (TFETs) reported sub-60 mV/dec, but Si homo-junction TFETs show insufficient on-current due to the poor tunneling probability of indirect-band gap materials. As tunneling probability at the p-i junction influences the on-current of TFETs, III-V compound semiconductors, which have a direct small band gap and low effective masses, are the most promising materials to achieve high tunneling current with SS below 60 mV/dec. Also, the tunneling current can be remarkably increased by forming a staggered or broken gap by choosing materials with different band offsets. Since the tunneling at a p-i junction is the current source of TFET devices, many researchers have reported the performance of TFETs fabricated from III-V wafers with high p-type doping concentration grown by the molecular beam epitaxy (MBE) method. However, very few InGaAs TFET devices fabricated on MOCVD-grown epitaxial layers have been reported due to the challenging techniques for achieving p-type InGaAs with high doping concentration and steep dopant profile. Accordingly, this work demonstrates the metal-organic chemical vapor deposition (MOCVD) growth techniques to grow a high-quality epitaxial layer for TFET device fabrication. Homo-junction p-i-n InGaAs epitaxial layers were grown for conventional TFET devices, and hetero-junction p++-Ge/i-InGaAs/n+-InAs nanowires were grown to confirm the possibility of boosting the TFET device performance. The TFET device performance at both epitaxial layers was characterized to confirm the potential of TFET devices fabricated on the epitaxy layers grown by the MOCVD method. The high-quality epitaxial layers were grown using the MOCVD method. Compared to the MBE method, cost-effectiveness, high throughput, and excellent crystal quality are the significant advantages of the MOCVD method. The growth of InGaAs film layers on InP (001) substrate with several growth conditions was studied. The effects of source flow rate, temperature, and V/III ratio on the quality of grown InGaAs film layers were studied. As the high-concentration and steep dopant profile of n-type and p-type dopants are challenging in MOCVD InGaAs growth technique, carbon and tellurium doping techniques were introduced to achieve highly-doped p-type and n-type InGaAs layer with steep dopant profile. The grown epitaxial film layers were evaluated by fabricating the TFET device. Before the TFET device fabrication, the dimensions of the TFET device were selected by electrical simulation results of TFET devices with different structures. For TFET device fabrication, a high-quality vertical p-i-n epitaxial structure with a steep doping profile was successively formed by MOCVD. After epitaxial growth, the TFET devices were fabricated by the vertical top-down wet etching method. The ohmic process and air-bridge process were also optimized for device fabrication. The effect of p-type doping concentration and the dislocations formed during MOCVD growth was confirmed by TFET performance. The fabricated TFET devices showed SS of near-60 mV/dec and sound on/off current ratio, which was by far the first reported device comparable to TFET devices fabricated on the MBE-grown wafers. This result represents the possible mass-production of high-quality MOCVD-grown III-V TFET devices. The next part of this study is nanowire TFET fabrication. The growth of III-V nanowires for electronic device fabrication has several advantages. The significant advantage is that hetero-structures with various characteristics can be formed on various wafers. The nanowires grown by a sufficiently small diameter show a dislocation-free interface even if nanowires have a different lattice constant compared to the wafer. Various types of band-alignment can be formed, and this is a crucial factor in boosting the tunneling current of TFETs. Also, nanowires with a small diameter show better device density in a chip, improved gate controllability, and enhanced throughput by reducing growth time. The InGaAs nanowires were grown by the selective area growth (SAG) method. As a hard-mask layer, a SiO2 layer was deposited on InP (111)B and Ge (111) wafers. Growth conditions far different from InGaAs film layer growth were tested due to the different growth modes. Selective growth of nanowires was identified by optimizing temperature, V/III ratio, and source flow rate. As a result, InAs and InGaAs nanowires were successfully grown on InP (111)B and Ge (111) wafers. For p-type material, the p++-doped Ge (111) wafer was used. The intrinsic InGaAs and InAs nanowires were selectively grown on the patterned substrate. Finally, n-type InAs nanowires with silicon dopant were grown subsequently. The grown nanowires were evaluated by fabricating the vertical nanowire TFETs. ALD HfO2 and ALD TiN processes were optimized for high step coverage and good interface state density. By applying the developed ALD processes, a successful demonstration of vertical nanowire Ge/InGaAs hetero-junction TFET was observed.Contents List of Tables List of Figures Chapter 1. Introduction 1 1.1. Backgrounds 1 1.2. III-V TFETs for Low Power Device 5 1.3. Epitaxy of III-V Materials 12 1.4. Research Aims 17 1.5. References 20 Chapter 2. Epitaxial Growth of InGaAs on InP (001) Substrate 24 2.1. Introduction 24 2.2. Temperature Dependent Properties of Intrinsic-InGaAs on InP (001) Substrate 33 2.3. In-situ Doping Properties of InGaAs on InP (001) Substrate 37 2.4. Conclusion 51 2.5. References 52 Chapter 3. Demonstration of TFET Device Fabricated on InGaAs-on-InP (001) Substrate 56 3.1. Introduction 56 3.2. Simulation of Basic Operations of TFET Device 60 3.3. Process Optimization of TFET Fabrication 68 3.4. Process Flow 74 3.5. Characterization of TFETs Fabricated on MBE-grown and MOCVD-grown Wafers 78 3.6. Conclusion 96 3.7. References 97 Chapter 4. Selective Area Growth of In(Ga)As Nanowires 101 4.1. Introduction 101 4.2. Process Flow of Nanowire Growth 108 4.3. Impact of Different Growth Variables on the Growth of InAs Nanowires 113 4.4. Impact of Different Growth Variables on the Growth of InGaAs Nanowires 127 4.5. Conclusion 144 4.6. References 146 Chapter 5. Demonstration of Vertical Nanowire TFET 149 5.1. Introduction 149 5.2. Optimization of ALD HfO2 High-k Stack 152 5.3. Optimization of ALD TiN Gate Metal 169 5.4. Detailed Demonstration of Vertical Nanowire TFET Fabrication Processes 182 5.5. Characterization of Fabricated Vertical Nanowire TFETs 196 5.6. Conclusion 203 5.7. References 205 Chapter 6. Conclusions and Outlook 209 6.1. Conclusions 209 6.2. Outlook 211 Appendix. 213 A. n+-InAs Nanowire Doping Concentration Evaluation by TLM Method 213 B. n+-InAs Nanowire Doping Concentration Evaluation by C-V Method 219 C. References 205 Abstract in Korean 226 Research Achievements 230๋ฐ•

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