Investigation of high-K gate dielectrics for advanced CMOS application

Ph.DDOCTOR OF PHILOSOPH

CONSIDERATION OF CONDUCTION MECHANISMS IN HIGH-K DIELECTRIC STACKS AS A TOOL TO STUDY ELECTRICALLY ACTIVE DEFECTS

In this paper conduction mechanisms which could govern the electron transport through high-k dielectrics are summarized. The influence of various factors – the type of high-k dielectric and its thickness; the doping with a certain element; the type of metal electrode as well as the measurement conditions (bias, polarity and temperature), on the leakage currents and dominant conduction mechanisms have been considered. Practical hints how to consider different conduction mechanisms and to differentiate between them are given. The paper presents an approach to assess important trap parameters from investigation of dominant conduction mechanisms

Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out

FLASH MEMORY DEVICES WITH METAL FLOATING GATE/METAL NANOCRYSTALS AS THE CHARGE STORAGE LAYER: A STATUS REVIEW

Traditional flash memory devices consist of Polysilicon Control Gate (CG) – Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) – Polysilicon Floating Gate (FG) – Silicon Oxide (Tunnel dielectric) – Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect.  Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer

Lanthanoid based materials in advanced CMOS technology

Ph.DDOCTOR OF PHILOSOPH

PHYSICAL MODELING OF ELECTRICAL AND DIELECTRIC PROPERTIES OF HIGH-k Ta2O5 BASED MOS CAPACITORS ON SILICON

In this paper we present an integral physical model for describing electrical and dielectric properties of MOS structures containing dielectric stack composed of a high-k dielectric (with emphasize on pure and doped Ta2O5) and an interfacial silicon dioxide or silicon oxynitride layer. Based on the model, an equivalent circuit of the structure is proposed. Validity of the model was demonstrated for structures containing different metal gates (Al, Au, Pt, W, TiN, Mo) and different Ta2O5 based high-k dielectrics, grown of bare or nitrided silicon substrates.The model describes very well the I-V characteristics of the considered structures, as well as frequency dependence of the capacitance in accumulation. Stress-induced leakage currents are also effectively analyzed by the use of the model

Electrical properties of ultra thin Al2O3 and HfO2 films as gate dielectrics in MOS technology

The rapidly evolving silicon industry demands devices with high-speed and low power consumption. This has led to aggressive scaling of the dimensions in metal oxide semiconductor field effect transistors (MOSFETs). The channel length has been reduced as a result of this scaling. The industry favorite, SlO2, has reached limitations in the thickness regime of 1-1.5 nm as a gate dielectric. High-κ gate dielectrics such as Al203 and HfO2 and their silicates are some of the materials that may, probably, replace SlO2, as gate dielectric in the next four to five years. The present study is an attempt to understand the electrical characteristics of these exciting materials grown by atomic layer deposition (ALD) technique. The flat band voltages (VFB) were determined from C-V measurements on circularly patterned MOS capacitors. For phosphorous doped polysilicon electrodes and Al-oxide based dielectrics, positive shifts in VFB were observed, relative to a pure SlO2 control, ranging from 0.2 to 0.8V. It is believed that this is caused by fixed charges. Rapid thermal annealing at 1000°C tends to decrease VFB relative to a 800°C anneal. Changes in VFB UP to 0.35 V are observed for films deposited over SlO2 underlayers, while smaller changes, up to 0.05 V, are observed for films deposited directly on Si. Spike annealing is also observed to reduce oxide leakage. HfO2 showed large amount of leakage resulting in difficulty in performing capacitance measurements. ZrO2 was found to be reacting with polycrystalline silicon and thus high leakage current was observed

Investigation of Energy Barrier Heights within Metal-insulator-metal Devices via Internal Photoemission Spectroscopy

Metal-insulator-metal (MIM) and dual-insulator MIM (MIIM) devices are used in rectennas, hot-electron transistors, single electron transistors, resistive random access memory (RRAM), and capacitors. The performance of these devices relies heavily on the energy barrier height at each metal-insulator interface. Thus, determination of the in-situ electron energy barrier at each interface is critical to accurately predicting charge transport and confidently integrating new materials into microelectronic devices. Internal photoemission (IPE) spectroscopy is a well-established electro-optical technique that allows for direct measurement of interfacial energy barriers within a device structure. Although IPE has widely been used to characterize the interfaces between various polycrystalline elemental metals and oxides within MOS structures, there have been relatively few reports of IPE within MIM structures. First, MIM structures with amorphous metal bottom electrodes are investigated via IPE. Amorphous metals are attractive for use in the aforementioned devices owing to their ultra-low roughness which gives rise to a highly uniform electric field in the ultrathin sandwiched insulator(s). IPE is used to measure the energy barrier heights in MIM device structures between either amorphous metal ZrCuAlNi, Ta-based amorphous metals (TaNiSi and TaWSi), or polycrystalline TaN and insulators deposited via atomic layer deposition (ALD). It is found that the Ta-based amorphous metals exhibit the largest barrier heights. The effect on the barrier height of a number of interfacial non-idealities are explored, including an interfacial ZrOx layer on ZrCuAlNi. A comparison is also made between Al and Au top electrodes for devices with a TaWSi bottom electrode, unexpectedly showing an effect of the top electrode on the bottom electrode barrier height. It is found that IPE energy barriers are consistent with current-voltage asymmetry of MIM diodes, whereas ideal Schottky model predictions of barrier heights were inconsistent. Next, ALD ruthenium top electrodes are investigated in both MIM and MOS structures. ALD metals such as ruthenium are promising electrode materials with growing interest for applications that require conformal, pinhole free conductive films, particularly for high aspect-ratio structures. Ru, due to relatively low bulk resistivity, high work function, a conductive oxide (RuO2), and ease of etching, is of interest as a gate electrode for MOS transistors, metal-insulator-metal (MIM) capacitors, RRAM, and tunnel diodes, as well as a conductive Cu diffusion barrier/liner for Cu interconnects. IPE is used to directly measure the φBn between ALD dielectrics Al2O3 and HfO2 and ALD Ru, both as-deposited and after a post-metallization anneal. Large barrier heights are found, supporting use of Ru as a gate electrode. It is found that barrier heights are relatively unaffected by the post-metallization anneal. The effects of interfacial oxides and interfacial charge trapping on the measured barrier heights are discussed. IPE is also utilized to study ALD ferroelectric HfZrOx. There has been increasing interest in ferroelectric materials for non-volatile memory applications. Barrier heights at the interface of ALD ferroelectric HfZrOx films and various metals are determined within MIM structures on TaN bottom electrodes. Knowledge of these technologically relevant barrier heights will assist in integration of ALD ferroelectric HfZrOx into non-volatile memory devices. Finally, bi-layer stacks of Al2O3 and Ta2O5 with differing ratios are characterized with current-voltage analysis and preliminary IPE measurements. Conduction mechanisms are proposed for all regions of current-voltage behavior and it is found that device performance may be engineered using the relative thicknesses of the insulators. Preliminary IPE results suggest that the insulator offset within the MIIM device may be determined using a standard IPE approach