4,406 research outputs found
Adaptive Planning Search Algorithm for Analog Circuit Verification
Integrated circuit verification has gathered considerable interest in recent
times. Since these circuits keep growing in complexity year by year,
pre-Silicon (pre-SI) verification becomes ever more important, in order to
ensure proper functionality. Thus, in order to reduce the time needed for
manually verifying ICs, we propose a machine learning (ML) approach, which uses
less simulations. This method relies on an initial evaluation set of operating
condition configurations (OCCs), in order to train Gaussian process (GP)
surrogate models. By using surrogate models, we can propose further, more
difficult OCCs. Repeating this procedure for several iterations has shown
better GP estimation of the circuit's responses, on both synthetic and real
circuits, resulting in a better chance of finding the worst case, or even
failures, for certain circuit responses. Thus, we show that the proposed
approach is able to provide OCCs closer to the specifications for all circuits
and identify a failure (specification violation) for one of the responses of a
real circuit
A generic debug interface for IP-integrated assertions
Der Entwurf von Hardware/Software Systemen ist auf eine solide
Verifikationsmethodik angewiesen, die den ganzen Design Flow durchzieht.
Viele Konzepte haben eine Erhöhung des Abstraktionsniveaus bei der
Entwurfseingabe gemeinsam, wobei der modell-basierte Hardware-Entwurf einen
vielversprechenden und sich verbreitenenden Ansatz darstellt. Assertion
basierte Verifikation ermöglicht dem Entwickler die Spezifikation von
Eigenschaften des Entwurfes und die Aufdeckung von Fällen, in denen diese
verletzt werden. Während Assertions in Entwurfs- und Simulationsstadien
weit verbreitet sind, ist der Ansatz, diese mit auf dem integrierten
Schaltkreis (IC) zu fertigen, neuartig. In dieser Diplomarbeit soll ein von
Infineon Technologies entwickeltes, auf UML basierendes Datenmodell,
welches zur Erfassung von Entwurfsspezifikation und zur automatischen
Code-Generierung genutzt wird dahingehend erweitert werden, die
Beschreibung für im IC integrierte Assertions zu ermöglichen. Für diese
Zwecke wird ein abstraktes Datenmodell beschrieben werden. Das Assertion
Interface soll die spezifikationsgetreue Modellintegration gewährleisten,
sowie IC interne Assertionresultate dem umgebenen System über das Interface
zugänglich machen und damit zum Debugging während der Laufzeit ermöglichen.
Ferner werden die Codegenerierungs Templates erläutert und
einBeispielsystem eingeführt, um die beschriebenden Konzepte zu validieren.Nowadays electronic systems design requires fast time to market and solid verification throughout the entire design flow. Many concepts have been researched to raise the level of abstraction during the design entry phase, whereas model-based design is the most promising one. Assertion-based verification enables the developer to specify properties of the design and to get report if these are violated. Assertions are common during development and simulation of electronic products but often are not included in the final silicon. In this thesis an UML-based model defined at Infineon Technologies for capturing design specification information and to generate code automatically using templates, will be extended to allow the description of an abstract debuggable assertion interface for silicon assertions. With help of the assertion interface it shall be possible to verify the correct module integration and to monitor IP-internal assertion checker results. Besides, the code-generation templates for the assertion interface model will be described. To demonstrate the usability of the developed concepts an example system will be introduced to validate the approach.Ilmenau, Techn. Univ., Diplomarbeit, 200
AI/ML Algorithms and Applications in VLSI Design and Technology
An evident challenge ahead for the integrated circuit (IC) industry in the
nanometer regime is the investigation and development of methods that can
reduce the design complexity ensuing from growing process variations and
curtail the turnaround time of chip manufacturing. Conventional methodologies
employed for such tasks are largely manual; thus, time-consuming and
resource-intensive. In contrast, the unique learning strategies of artificial
intelligence (AI) provide numerous exciting automated approaches for handling
complex and data-intensive tasks in very-large-scale integration (VLSI) design
and testing. Employing AI and machine learning (ML) algorithms in VLSI design
and manufacturing reduces the time and effort for understanding and processing
the data within and across different abstraction levels via automated learning
algorithms. It, in turn, improves the IC yield and reduces the manufacturing
turnaround time. This paper thoroughly reviews the AI/ML automated approaches
introduced in the past towards VLSI design and manufacturing. Moreover, we
discuss the scope of AI/ML applications in the future at various abstraction
levels to revolutionize the field of VLSI design, aiming for high-speed, highly
intelligent, and efficient implementations
Flat-plate solar array project. Volume 5: Process development
The goal of the Process Development Area, as part of the Flat-Plate Solar Array (FSA) Project, was to develop and demonstrate solar cell fabrication and module assembly process technologies required to meet the cost, lifetime, production capacity, and performance goals of the FSA Project. R&D efforts expended by Government, Industry, and Universities in developing processes capable of meeting the projects goals during volume production conditions are summarized. The cost goals allocated for processing were demonstrated by small volume quantities that were extrapolated by cost analysis to large volume production. To provide proper focus and coverage of the process development effort, four separate technology sections are discussed: surface preparation, junction formation, metallization, and module assembly
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