A Low Density Lattice Decoder via Non-Parametric Belief Propagation

The recent work of Sommer, Feder and Shalvi presented a new family of codes called low density lattice codes (LDLC) that can be decoded efficiently and approach the capacity of the AWGN channel. A linear time iterative decoding scheme which is based on a message-passing formulation on a factor graph is given. In the current work we report our theoretical findings regarding the relation between the LDLC decoder and belief propagation. We show that the LDLC decoder is an instance of non-parametric belief propagation and further connect it to the Gaussian belief propagation algorithm. Our new results enable borrowing knowledge from the non-parametric and Gaussian belief propagation domains into the LDLC domain. Specifically, we give more general convergence conditions for convergence of the LDLC decoder (under the same assumptions of the original LDLC convergence analysis). We discuss how to extend the LDLC decoder from Latin square to full rank, non-square matrices. We propose an efficient construction of sparse generator matrix and its matching decoder. We report preliminary experimental results which show our decoder has comparable symbol to error rate compared to the original LDLC decoder.%Comment: Submitted for publicatio

Low Density Lattice Codes

Low density lattice codes (LDLC) are novel lattice codes that can be decoded efficiently and approach the capacity of the additive white Gaussian noise (AWGN) channel. In LDLC a codeword x is generated directly at the n-dimensional Euclidean space as a linear transformation of a corresponding integer message vector b, i.e., x = Gb, where H, the inverse of G, is restricted to be sparse. The fact that H is sparse is utilized to develop a linear-time iterative decoding scheme which attains, as demonstrated by simulations, good error performance within ~0.5dB from capacity at block length of n = 100,000 symbols. The paper also discusses convergence results and implementation considerations.Comment: 24 pages, 4 figures. Submitted for publication in IEEE transactions on Information Theor

Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approxi- mated to a single Gaussian. A detailed quantization study is first performed to find the minimum number of bits required for the fixed-point decoder to attain a frame error rate (FER) performance similar to floating-point. Then efficient numeri- cal methods are devised to approximate the required non-linear functions. Finally, the paper presents a comparison of the performance of the different decoder architectures as well as a detailed analysis of the resource requirements and through- put trade-offs of the primary design blocks for the different architectures. A novel pipelined LDLC decoder architecture is proposed where resource re-utilization along with pipelining allows for a parallelism equivalent to 50 variable nodes on the target FPGA device. The pipelined architecture attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 1.8× improvement in throughput compared to an implementation with 20 parallel variable nodes without pipelining. This implementation also achieves 24× improvement in throughput over a baseline serial decoder.NSERC || CMC Microsystem

Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes

Low-density lattice codes (LDLCs) are a special class of lattice codes that can be decoded efficiently using iterative decoding and approach the capacity of the additive white Gaussian noise (AWGN) channel. The construction and intended applications are substantially different from that of more familiar error-correcting codes such as low-density parity check (LDPC) codes, Polar, and Turbo codes. Lattice codes in general have shown great theoretical promise to mitigate interference, possibly leading to significantly higher rates between users in multi-user networks. Research on LDLCs has concentrated on demonstrating the theoretically achievable performance limits of LDLCs, and until now there has been no reported hardware implementation, mainly due to the complexity of message-passing for LDLC decoding. This thesis contributes to the hardware implementation of the LDLC decoding. We present several fixed-point decoder implementations covering different parts of the architectural design space, on a field-programmable gate array (FPGA) device. We first present the FPGA implementation of a fixed-point arithmetic LDLC decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is performed to find the minimum number of bits required for the fixed-point decoder implementation to attain a frame-error-rate (FER) performance similar to floating-point. Efficient numerical methods are used to approximate the non-linear functions required in the decoder. A two-node serial LDLC decoder is implemented on an Intel Arria 10 FPGA as a hardware proof-of-concept attaining a throughput of 440 Ksymbols/sec at high signal-to-noise ratio (SNR). This throughput is obtained at clock frequency of 125 MHz and for a block length of 1000. By exploiting the inherent parallelism of iterative decoding, several parallel message processing blocks are then used to improve the throughput by a factor of 13x. Finally, we propose a pipelined architecture where the decoder achieves a throughput of 10.5 Msymbols/sec, that is, ~24x improvement over the serial decoder. Then, we implement a multi-Gaussian decoder where the Gaussian mixture messages exchanged during the decoding process have two components. We develop efficient techniques to reduce the decoder complexity for hardware implementation, e.g., selecting the strongest component from the Gaussian mixture as the final decision in iterative decoding, and a simplified method for coefficient computation during the product operation at the variable nodes. With a thorough quantization analysis and applying methods devised to approximate the non-linear functions, we design the multi-Gaussian decoders in fixed point arithmetic. We first implemented a serial architecture with a single check node and a single variable node. Then, a partially parallel architecture with a single check node and a variable node message processing block with two-stage pipelining is implemented to achieve an effective parallelism of 5 variable nodes. The pipelined architecture achieves an improvement of ~0.75 dB in decoding performance over the single Gaussian decoder of degree 3 with an overall design throughput of 550 Ksymbols/sec. In the final part of the thesis, we further explore the design space and develop complex LDLC decoder designs for higher degrees. We characterize the decoding performance of these decoders and present the design throughputs for different architectures on the target FPGA. Based on these results, we provide insights that will help users to select the most suitable LDLC decoder for a particular application. However this is attained with additional hardware cost and reduced design throughput. A single-Gaussian decoder of degree 7 achieved an FER improvement of 0.75 dB over a single-Gaussian decoder of degree 3 with a throughput of 3.03 Msymbols/sec. The multi-Gaussian Gaussian decoder of degree 7 (with two components in the Gaussian mixture) attains 1.75 dB improvement in FER over the multi-Gaussian decoder of degree 3, and its overall design throughput is ~84 Ksymbols/sec. From a broader perspective, the LDLC decoders with higher degrees and larger mixture messages provide a significant improvement in decoding performance. For ultra-reliable applications, a multi-Gaussian decoder of degree 7 is most suitable while for a very high throughput requirement single-Gaussian decoder of degree 3 is the best choice. We also characterize the performance of multi-Gaussian decoders where the Gaussian mixture messages contain more than two components. Based on the results, the multi- Gaussian decoder with mixture messages that contain 5 components gain approximately ~0.1 - 0.2 dB (for degree 3 and 7) and ~0.3 dB (for degree 5) over multi-Gaussian decoder where mixture messages have only two components

Lattice-Based Coding Schemes for Wireless Relay Networks

Compute-and-forward is a novel relaying paradigm in wireless communications in which relays in a network directly compute or decode functions of signals transmitted from multiple transmitters and forward them to a central destination. In this dissertation, we study three problems related to compute-and-forward. In the first problem, we consider the use of lattice codes for implementing a compute-and-forward protocol in wireless networks when channel state information is not available at the transmitter. We propose the use of lattice codes over Eisenstein integers and we prove the existence of a sequence of lattices over Eisenstein integers which are good for quantization and achieve capacity over an additive white Gaussian noise (AWGN) channel. Using this, we show that the information rates achievable with nested lattice codebooks over Eisenstein integers are higher than those achievable with nested lattice codebooks over integers considered by Nazer and Gastpar in [6] in the average sense. We also propose a separation-based framework for compute-and-forward that is based on the concatenation of a non-binary linear code with a modulation scheme derived from the ring of Eisenstein integers, which enables the coding gain and shaping gain to be separated, resulting in significantly higher theoretically achievable computation rates. In the second problem, we construct lattices based on spatially-coupled low-density parity check (LDPC) codes and empirically show that such lattices can approach the Poltyrev limit very closely for the point-to-point unconstrained AWGN channel. We then employ these lattices to implement a compute-and-forward protocol and empirically show that these lattices can approach the theoretically achievable rates closely. In the third problem, we present a new coding scheme based on concatenating a newly introduced class of lattice codes called convolutional lattice codes with LDPC codes, which we refer to as concatenated convolutional lattice codes (CCLS) and study their application to compute-and-forward (CF). The decoding algorithm for CCLC is based on an appropriate combination of the stack decoder with a message passing algorithm, and is computationally much more efficient than the conventional decoding algorithm for convolutional lattice codes. Simulation results show that CCLC can approach the point-to-point uniform input AWGN capacity very closely with soft decision decoding. Also, we show that they possess the required algebraic structure which makes them suitable for recovering linear combinations (over a finite field) of the transmitted signals in a multiple access channel. This facilitates their use as a coding scheme for the compute-and-forward paradigm. Simulation results show that CCLC can approach theoretically achievable rates very closely when implemented for the compute-and-forward

Low-dimensional Lattice Codes for Bidirectional Relaying

We consider a communication system where two transmitters wish to exchange information through a central relay. The data is assumed to be transmitted over synchronized, average power constrained additive white Gaussian noise channels with a real input with signal-to-noise ratio (SNR) of snr. It has been shown that using lattice codes and lattice decoding, a rate of 1/2 log_2(1/2 plus snr) can be obtained asymptotically, which is essentially optimal at high SNR. However, there has been a lack of practical encoding/decoding schemes for the above mentioned system. We address this issue in this thesis by developing encoding/decoding strategies for the bidirectional relaying system using low-dimensional lattice codes. Our efforts are aimed at developing coding schemes which possess low computational complexity while at the same time providing good performance. We demonstrate two schemes using low-dimensional lattice codes. Both these schemes have their own advantages and are suitable for different classes of lattice codes. The two schemes are tested with different lattices and their performance is compared to that of other schemes for bidirectional relays. The first scheme is termed as demodulate and forward and it essentially consists of performing optimal estimation at the relay. It is primarily implemented with lattice codes of low rate and possesses low decoding complexity. When used with a two-dimensional hexagonal lattice, it achieves a gain of around 3.5 dB in comparison to other schemes like Analog network coding. The second scheme is the sphere decoding scheme which has been implemented with high-rate lattice codes. The sphere decoder is a low-complexity decoder which is used for decoding to a lattice point at the relay. We observe that as the dimensionality of the lattice code is increased, the performance of the sphere decoder for the bidirectional relay gets consistently better. The sphere decoder is also used at high SNR for those instances in which the low density lattice code(LDLC) decoder makes an error and it is found that the sphere decoder can correct around 90 percent of these errors at an SNR of 9.75 dB