131 research outputs found

    Spinal codes

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    Spinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits to produce a sequence of coded symbols for transmission. This encoding ensures that two input messages that differ in even one bit lead to very different coded sequences after the point at which they differ, providing good resilience to noise and bit errors. To decode spinal codes, this paper develops an approximate maximum-likelihood decoder, called the bubble decoder, which runs in time polynomial in the message size and achieves the Shannon capacity over both additive white Gaussian noise (AWGN) and binary symmetric channel (BSC) models. Experimental results obtained from a software implementation of a linear-time decoder show that spinal codes achieve higher throughput than fixed-rate LDPC codes, rateless Raptor codes, and the layered rateless coding approach of Strider, across a range of channel conditions and message sizes. An early hardware prototype that can decode at 10 Mbits/s in FPGA demonstrates that spinal codes are a practical construction.Massachusetts Institute of Technology (Irwin and Joan Jacobs Presidential Fellowship)Massachusetts Institute of Technology (Claude E. Shannon Assistantship)Intel Corporation (Intel Fellowship

    Near-capacity fixed-rate and rateless channel code constructions

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    Fixed-rate and rateless channel code constructions are designed for satisfying conflicting design tradeoffs, leading to codes that benefit from practical implementations, whilst offering a good bit error ratio (BER) and block error ratio (BLER) performance. More explicitly, two novel low-density parity-check code (LDPC) constructions are proposed; the first construction constitutes a family of quasi-cyclic protograph LDPC codes, which has a Vandermonde-like parity-check matrix (PCM). The second construction constitutes a specific class of protograph LDPC codes, which are termed as multilevel structured (MLS) LDPC codes. These codes possess a PCM construction that allows the coexistence of both pseudo-randomness as well as a structure requiring a reduced memory. More importantly, it is also demonstrated that these benefits accrue without any compromise in the attainable BER/BLER performance. We also present the novel concept of separating multiple users by means of user-specific channel codes, which is referred to as channel code division multiple access (CCDMA), and provide an example based on MLS LDPC codes. In particular, we circumvent the difficulty of having potentially high memory requirements, while ensuring that each user’s bits in the CCDMA system are equally protected. With regards to rateless channel coding, we propose a novel family of codes, which we refer to as reconfigurable rateless codes, that are capable of not only varying their code-rate but also to adaptively modify their encoding/decoding strategy according to the near-instantaneous channel conditions. We demonstrate that the proposed reconfigurable rateless codes are capable of shaping their own degree distribution according to the nearinstantaneous requirements imposed by the channel, but without any explicit channel knowledge at the transmitter. Additionally, a generalised transmit preprocessing aided closed-loop downlink multiple-input multiple-output (MIMO) system is presented, in which both the channel coding components as well as the linear transmit precoder exploit the knowledge of the channel state information (CSI). More explicitly, we embed a rateless code in a MIMO transmit preprocessing scheme, in order to attain near-capacity performance across a wide range of channel signal-to-ratios (SNRs), rather than only at a specific SNR. The performance of our scheme is further enhanced with the aid of a technique, referred to as pilot symbol assisted rateless (PSAR) coding, whereby a predetermined fraction of pilot bits is appropriately interspersed with the original information bits at the channel coding stage, instead of multiplexing pilots at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We subsequently demonstrate that the PSAR code-aided transmit preprocessing scheme succeeds in gleaning more information from the inserted pilots than the classic PSAM technique, because the pilot bits are not only useful for sounding the channel at the receiver but also beneficial for significantly reducing the computational complexity of the rateless channel decoder

    Unequal Error Protection Raptor Codes

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    We design Unequal Error Protection (UEP) Raptor codes with the UEP property provided by the precode part of Raptor codes which is usually a Low Density Parity Check (LDPC) code. Existing UEP Raptor codes apply the UEP property on the Luby transform (LT) code part of Raptor codes. This approach lowers the bit erasure rate (BER) of the more important bits (MIB) of the data decoded by the LT part of the decoder of Raptor code at the expense of degrading the BER performance of Less Important Bits (LIB), and hence the overall BER of the data passed from the LT part to the LDPC part of the decoder is higher compared to the case of using an Equal Error Protection (EEP) LT code. The proposed UEP Raptor code design has the structure of UEP LDPC code and EEP LT code so that it has the advantage of passing data blocks with lower BER from the LT code part to the LDPC code part of the decoder. This advantage is translated into improved performance in terms of required overhead and achieved BER on both the MIB bits and LIB bits of the decoded data compared to UEP Raptor codes applying the UEP property on the LT part. We propose two design schemes. The first combines a partially regular LDPC code which has UEP properties with an EEP LT code, and the second scheme uses two LDPC codes with different code rates in the precode part such that the MIB bits are encoded using the LDPC code with lower rate and the LT part is EEP. Simulations of both designs exhibit improved BER performance on both the MIB bits and LIB bits while consuming smaller overheads. The second design can be used to provide unequal protection for cases where the MIB bits comprise a fraction of more than 0.4 of the source data which is a case where UEP Raptor codes with UEP LT codes perform poorly

    Link-Layer Coding for GNSS Navigation Messages

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    In this paper, we face the problem of ensuring reliability of Global Navigation Satellite Systems (GNSSs) in harsh channel conditions, where obstacles and scatter cause long outage events that cannot be counteracted with channel coding only. Our novel approach, stemming from information-theoretic considerations, is based on link-layer coding (LLC). LLC allows us to significantly improve the efficiency in terms of time-to-first-fix with respect to current operational GNSSs, which adopt carousel transmission. First, we investigate the maximum theoretical LLC gain under different Land Mobile Satellite channel conditions. Then, some practical LLC coding schemes, namely, fountain codes and a novel low-density parity-check plus low-rate repetition coding, are proposed and tested in realistic single-satellite and multi-satellite Land Mobile Satellite scenarios, considering the Galileo I/NAV message as study case. Simulation results show that our designed schemes largely improve on carousel transmission and achieve near-optimal performance with limited increase in complexity. Also, back-compatibility of LLC is assessed with respect to present-time GNSS specifications. © 2018 Institute of Navigation

    Concatenated Turbo/LDPC codes for deep space communications: performance and implementation

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    Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work proposes a scheme based on the concatenation of non-custom LDPC and turbo codes that achieves excellent error correction performance. Moreover, since both LDPC and turbo codes can be decoded with the BCJR algorithm, our preliminary results show that an efficient hardware architecture with high resource reuse can be designe
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