A Triple-Memristor Hopfield Neural Network With Space Multi-Structure Attractors And Space Initial-Offset Behaviors

© 2023 IEEE. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCAD.2023.3287760Memristors have recently demonstrated great promise in constructing memristive neural networks with complex dynamics. This paper proposes a memristive Hopfield neural network with three memristive coupling synaptic weights. The complex dynamical behaviors of the triple-memristor Hopfield neural network (TM-HNN), which have never been observed in previous Hopfield-type neural networks, include space multi-structure chaotic attractors and space initial-offset coexisting behaviors. Bifurcation diagrams, Lyapunov exponents, phase portraits, Poincaré maps, and basins of attraction are used to reveal and examine the specific dynamics. Theoretical analysis and numerical simulation show that the number of space multi-structure attractors can be adjusted by changing the control parameters of the memristors, and the position of space coexisting attractors can be changed by switching the initial states of the memristors. Extreme multistability emerges as a result of the TM-HNN’s unique dynamical behaviors, making it more suitable for applications based on chaos. Moreover, a digital hardware platform is developed and the space multi-structure attractors as well as the space coexisting attractors are experimentally demonstrated. Finally, we design a pseudo-random number generator to explore the potential application of the proposed TM-HNN.Peer reviewe

Memristors for the Curious Outsiders

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.Comment: Perpective paper for MDPI Technologies; 43 page

Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing

Functional Capabilities of Coupled Memristor-Based Reactance-Less Oscillators

New functionalities of reactance-less memristor based oscillators are discussed which arise when two elementary oscillators are connected. It is shown that the system of coupled memristor based oscillators can be used for converting analog and analog-digital signals into binary pulse sequences. The approach to control the thresholds in memristor based oscillators is discussed. Standard control approach in memristor based oscillators is the exploitation of input signal to drive the rate of change in the state of the memristor. In contrast, the main idea of the considered controlling approach is to send the input signal not directly to the memristor device but to the comparator circuit and as result to control oscillator circuit behavior by change of interval of memristor resistor variation. The capabilities of coupled memristor based oscillators with control thresholds are sufficient for constructing the simple circuit elements of oscillatory computing architectures

An overview of memristive cryptography

Smaller, smarter and faster edge devices in the Internet of things era demands secure data analysis and transmission under resource constraints of hardware architecture. Lightweight cryptography on edge hardware is an emerging topic that is essential to ensure data security in near-sensor computing systems such as mobiles, drones, smart cameras, and wearables. In this article, the current state of memristive cryptography is placed in the context of lightweight hardware cryptography. The paper provides a brief overview of the traditional hardware lightweight cryptography and cryptanalysis approaches. The contrast for memristive cryptography with respect to traditional approaches is evident through this article, and need to develop a more concrete approach to developing memristive cryptanalysis to test memristive cryptographic approaches is highlighted.Comment: European Physical Journal: Special Topics, Special Issue on "Memristor-based systems: Nonlinearity, dynamics and applicatio

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.Siirretty Doriast